ATMEGA324PA-MU中文资料

Features•High-performance,Low-powerAVR®8-bitMicrocontroller�AdvancedRISCArchitecture–131PowerfulInstructions–MostSingle-clockCycleExecution–32x8GeneralPurposeWorkingRegisters–FullyStaticOperation–Upto20MIPSThroughputat20MHz–On-chip2-cycleMultiplier�HighEnduranceNon-volatileMemorysegments–32KBytesofIn-SystemSelf-programmableFlashprogrammemory–1KBytesEEPROM–2KBytesInternalSRAM–Write/EraseCycles:10,000Flash/100,000EEPROM–Dataretention:20yearsat85°C/100yearsat25°C(1)–OptionalBootCodeSectionwithIndependentLockBitsIn-SystemProgrammingbyOn-chipBootProgramTrueRead-While-WriteOperation–ProgrammingLockforSoftwareSecurity�JTAG(IEEEstd.1149.1Compliant)Interface–Boundary-scanCapabilitiesAccordingtotheJTAGStandard–ExtensiveOn-chipDebugSupport–ProgrammingofFlash,EEPROM,Fuses,andLockBitsthroughtheJTAGInterface�PeripheralFeatures–Two8-bitTimer/CounterswithSeparatePrescalersandCompareModes–One16-bitTimer/CounterwithSeparatePrescaler,CompareMode,andCaptureMode–RealTimeCounterwithSeparateOscillator–SixPWMChannels–8-channel,10-bitADCDifferentialmodewithselectablegainat1x,10xor200x–Byte-orientedTwo-wireSerialInterface–TwoProgrammableSerialUSART–Master/SlaveSPISerialInterface–ProgrammableWatchdogTimerwithSeparateOn-chipOscillator–On-chipAnalogComparator–InterruptandWake-uponPinChange�SpecialMicrocontrollerFeatures–Power-onResetandProgrammableBrown-outDetection–InternalCalibratedRCOscillator–ExternalandInternalInterruptSources–SixSleepModes:Idle,ADCNoiseReduction,Power-save,Power-down,StandbyandExtendedStandby�I/OandPackages–32ProgrammableI/OLines–40-pinPDIP,44-leadTQFP,44-padVQFN/QFN/MLF–44-padDRQFN–49-ballVFBGA�OperatingVoltages–1.8-5.5V�SpeedGrades–0-20MHz@1.8-5.5V�PowerConsumptionat1MHz,1.8V,25°C–Active:0.4mA–Power-downMode:0.1µA–Power-saveMode:0.6µA(Including32kHzRTC)8-bitMicrocontrollerwith32KBytesIn-SystemProgrammableFlashATmega324PASummary8152AS–AVR–11/0828152AS–AVR–11/08ATmega324PA1.PinConfigurations1.1Pinout-PDIP/TQFP/VQFN/QFN/MLFFigure1-1.PinoutNote:ThelargecenterpadunderneaththeVQFN/QFN/MLFpackageshouldbesolderedtogroundontheboardtoensuregoodmechanicalstability.(PCINT8/XCK0/T0)PB0(PCINT9/CLKO/T1)PB1(PCINT10/INT2/AIN0)PB2(PCINT11/OC0A/AIN1)PB3(PCINT12/OC0B/SS)PB4(PCINT13/MOSI)PB5(PCINT14/MISO)PB6(PCINT15/SCK)PB7RESETVCCGNDXTAL2XTAL1(PCINT24/RXD0)PD0(PCINT25/TXD0)PD1(PCINT26/RXD1/INT0)PD2(PCINT27/TXD1/INT1)PD3(PCINT28/XCK1/OC1B)PD4(PCINT29/OC1A)PD5(PCINT30/OC2B/ICP)PD6PA0(ADC0/PCINT0)PA1(ADC1/PCINT1)PA2(ADC2/PCINT2)PA3(ADC3/PCINT3)PA4(ADC4/PCINT4)PA5(ADC5/PCINT5)PA6(ADC6/PCINT6)PA7(ADC7/PCINT7)AREFGNDAVCCPC7(TOSC2/PCINT23)PC6(TOSC1/PCINT22)PC5(TDI/PCINT21)PC4(TDO/PCINT20)PC3(TMS/PCINT19)PC2(TCK/PCINT18)PC1(SDA/PCINT17)PC0(SCL/PCINT16)PD7(OC2A/PCINT31)PDIPPA4(ADC4/PCINT4)PA5(ADC5/PCINT5)PA6(ADC6/PCINT6)PA7(ADC7/PCINT7)AREFGNDAVCCPC7(TOSC2/PCINT23)PC6(TOSC1/PCINT22)PC5(TDI/PCINT21)PC4(TDO/PCINT20)(PCINT13/MOSI)PB5(PCINT14/MISO)PB6(PCINT15/SCK)PB7RESETVCCGNDXTAL2XTAL1(PCINT24/RXD0)PD0(PCINT25/TXD0)PD1(PCINT26/RXD1/INT0)PD2(PCINT27/TXD1/INT1)PD3(PCINT28/XCK1/OC1B)PD4(PCINT29/OC1A)PD5(PCINT30/OC2B/ICP)PD6(PCINT31/OC2A)PD7VCCGND(PCINT16/SCL)PC0(PCINT17/SDA)PC1(PCINT18/TCK)PC2(PCINT19/TMS)PC3PB4(SS/OC0B/PCINT12)PB3(AIN1/OC0A/PCINT11)PB2(AIN0/INT2/PCINT10)PB1(T1/CLKO/PCINT9)PB0(XCK0/T0/PCINT8)GNDVCCPA0(ADC0/PCINT0)PA1(ADC1/PCINT1)PA2(ADC2/PCINT2)PA3(ADC3/PCINT3)TQFP/VQFN/QFN/MLF38152AS–AVR–11/08ATmega324PA1.2Pinout-DRQFNFigure1-2.DRQFN-PinoutTable1-1.DRQFN-PinoutA1PB5A7PD3A13PC4A19PA3B1PB6B6PD4B11PC5B16PA2A2PB7A8PD5A14PC6A20PA1B2RESETB7PD6B12PC7B17PA0A3VCCA9PD7A15AVCCA21VCCB3GNDB8VCCB13GNDB18GNDA4XTAL2A10GNDA16AREFA22PB0B4XTAL1B9PC0B14PA7B19PB1A5PD0A11PC1A17PA6A23PB2B5PD1B10PC2B15PA5B20PB3A6PD2A12PC3A18PA4A24PB4TopviewBottomviewA1B1A2B2A3B3A4B4A5B5A6A18B15A17B14A16B13A15B12A14B11A13A12B10A11B9A10B8A9B7A8B6A7A24B20A23B19A22B18A21B17A20B16A19A18B15A17B14A16B13A15B12A14B11A13A1B1A2B2A3B3A4B4A5B5A6A7B6A8B7A9B8A10B9A11B10A12A19B16A20B17A21B18A22B19A23B20A2448152AS–AVR–11/08ATmega324PA1.3Pinout-VFBGAFigure1-3.VFBGA-PinoutTable1-2.BGA-Pinout1234567AGNDPB4PB2GNDVCCPA2GNDBPB6PB5PB3PB0PA0PA3PA5CVCCRESETPB7PB1PA1PA6AREFDGNDXTAL2PD0GNDPA4PA7GNDEXTAL1PD1PD5PD7PC5PC7AVCCFPD2PD3PD6PC0PC2PC4PC6GGNDPD4VCCGNDPC1PC3GNDABCDEFG1234567ABCDEFG7654321TopviewBottomview58152AS–AVR–11/08ATmega324PA2.OverviewTheATmega324PAisalow-powerCMOS8-bitmicrocontrollerbasedontheAVRenhancedRISCarchitecture.Byexecutingpowerfulinstructionsinasingleclockcycle,theATmega324PAachievesthroughputsapproaching1MIPSperMHzallowingthesystemdesignertooptimizepowerconsumptionversusprocessingspeed.2.1BlockDiagramFigure2-1.BlockDiagramTheAVRcorecombinesarichinstructionsetwith32generalpurposeworkingregisters.Allthe32registersaredirectlyconnectedtotheArithmeticLogicUnit(ALU),allowingtwoindependentregisterstobeaccessedinonesingleinstructionexecutedinoneclockcycle.Theresultingarchitectureismorecodeefficientwhileachievingthroughputsuptotentimesfasterthancon-ventionalCISCmicrocontrollers.CPUGNDVCCRESETPowerSupervisionPOR/BOD&RESETWatchdogOscillatorWatchdogTimerOscillatorCircuits/ClockGenera