AT89C52-12JC中文资料

1Features•CompatiblewithMCS-51™Products8KBytesofIn-SystemReprogrammableFlashMemoryEndurance:1,000Write/EraseCyclesFullyStaticOperation:0Hzto24MHzThree-levelProgramMemoryLock256x8-bitInternalRAM32ProgrammableI/OLinesThree16-bitTimer/CountersEightInterruptSourcesProgrammableSerialChannelLow-powerIdleandPower-downModesDescriptionTheAT89C52isalow-power,high-performanceCMOS8-bitmicrocomputerwith8KbytesofFlashprogrammableanderasablereadonlymemory(PEROM).ThedeviceismanufacturedusingAtmel’shigh-densitynonvolatilememorytechnologyandiscompatiblewiththeindustry-standard80C51and80C52instructionsetandpinout.Theon-chipFlashallowstheprogrammemorytobereprogrammedin-systemorbyaconventionalnonvolatilememoryprogrammer.Bycombiningaversatile8-bitCPUwithFlashonamonolithicchip,theAtmelAT89C52isapowerfulmicrocomputerwhichprovidesahighly-flexibleandcost-effectivesolutiontomanyembeddedcontrolapplications.8-bitMicrocontrollerwith8KBytesFlashAT89C52NotRecommendedforNewDesigns.UseAT89S52.Rev.0313H–02/00PinConfigurationsPQFP/TQFP12345678910113332313029282726252423P1.5P1.6P1.7RST(RXD)P3.0NC(TXD)P3.1(INT0)P3.2(INT1)P3.3(T0)P3.4iT1)P3.5P0.4(AD4)P0.5(AD5)P0.6(AD6)P0.7(AD7)EA/VPPNCALE/PROGPSENP2.7(A15)P2.6(A14)P2.5(A13)44434241403938373635341213141516171819202122(WR)P3.6(RD)P3.7XTAL2XTAL1GNDNC(A8)P2.0(A9)P2.1(A10)P2.2(A11)P2.3(A12)P2.4P1.4P1.3P1.2P1.1(T2EX)P1.0(T2)NCVCCP0.0(AD0)P0.1(AD1)P0.2(AD2)P0.3(AD3)PDIP12345678910111213141516171819204039383736353433323130292827262524232221(T2)P1.0(T2EX)P1.1P1.2P1.3P1.4P1.5P1.6P1.7RST(RXD)P3.0(TXD)P3.1(INT0)P3.2(INT1)P3.3(T0)P3.4(T1)P3.5(WR)P3.6(RD)P3.7XTAL2XTAL1GNDVCCP0.0(AD0)P0.1(AD1)P0.2(AD2)P0.3(AD3)P0.4(AD4)P0.5(AD5)P0.6(AD6)P0.7(AD7)EA/VPPALE/PROGPSENP2.7(A15)P2.6(A14)P2.5(A13)P2.4(A12)P2.3(A11)P2.2(A10)P2.1(A9)P2.0(A8)PLCC78910111213141516173938373635343332313029P1.5P1.6P1.7RST(RXD)P3.0NC(TXD)P3.1(INT0)P3.2(INT1)P3.3(T0)P3.4(T1)P3.5P0.4(AD4)P0.5(AD5)P0.6(AD6)P0.7(AD7)EA/VPPNCALE/PROGPSENP2.7(A15)P2.6(A14)P2.5(A13)65432144434241401819202122232425262728(WR)P3.6(RD)P3.7XTAL2XTAL1GNDNC(A8)P2.0(A9)P2.1(A10)P2.2(A11)P2.3(A12)P2.4P1.4P1.3P1.2P1.1(T2EX)P1.0(T2)NCVCCP0.0(AD0)P0.1(AD1)P0.2(AD2)P0.3(AD3)AT89C522BlockDiagramPORT2DRIVERSPORT2LATCHP2.0-P2.7QUICKFLASHPORT0LATCHRAMPROGRAMADDRESSREGISTERBUFFERPCINCREMENTERPROGRAMCOUNTERDPTRRAMADDR.REGISTERINSTRUCTIONREGISTERBREGISTERINTERRUPT,SERIALPORT,ANDTIMERBLOCKSSTACKPOINTERACCTMP2TMP1ALUPSWTIMINGANDCONTROLPORT3LATCHPORT3DRIVERSP3.0-P3.7PORT1LATCHPORT1DRIVERSP1.0-P1.7OSCGNDVCCPSENALE/PROGEA/VPPRSTPORT0DRIVERSP0.0-P0.7AT89C523TheAT89C52providesthefollowingstandardfeatures:8KbytesofFlash,256bytesofRAM,32I/Olines,three16-bittimer/counters,asix-vectortwo-levelinterruptarchitecture,afull-duplexserialport,on-chiposcillator,andclockcir-cuitry.Inaddition,theAT89C52isdesignedwithstaticlogicforoperationdowntozerofrequencyandsupportstwosoftwareselectablepowersavingmodes.TheIdleModestopstheCPUwhileallowingtheRAM,timer/counters,serialport,andinterruptsystemtocontinuefunctioning.ThePower-downmodesavestheRAMcontentsbutfreezestheoscillator,disablingallotherchipfunctionsuntilthenexthardwarereset.PinDescriptionVCCSupplyvoltage.GNDGround.Port0Port0isan8-bitopendrainbi-directionalI/Oport.Asanoutputport,eachpincansinkeightTTLinputs.When1sarewrittentoport0pins,thepinscanbeusedashigh-impedanceinputs.Port0canalsobeconfiguredtobethemultiplexedlow-orderaddress/databusduringaccessestoexternalpro-gramanddatamemory.Inthismode,P0hasinternalpullups.Port0alsoreceivesthecodebytesduringFlashprogram-mingandoutputsthecodebytesduringprogramverification.Externalpullupsarerequiredduringprogramverification.Port1Port1isan8-bitbi-directionalI/Oportwithinternalpullups.ThePort1outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort1pins,theyarepulledhighbytheinternalpullupsandcanbeusedasinputs.Asinputs,Port1pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseoftheinternalpullups.Inaddition,P1.0andP1.1canbeconfiguredtobethetimer/counter2externalcountinput(P1.0/T2)andthetimer/counter2triggerinput(P1.1/T2EX),respectively,asshowninthefollowingtable.Port1alsoreceivesthelow-orderaddressbytesduringFlashprogrammingandverification.Port2Port2isan8-bitbi-directionalI/Oportwithinternalpullups.ThePort2outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort2pins,theyarepulledhighbytheinternalpullupsandcanbeusedasinputs.Asinputs,Port2pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseoftheinternalpullups.Port2emitsthehigh-orderaddressbyteduringfetchesfromexternalprogrammemoryandduringaccessestoexternaldatamemorythatuse16-bitaddresses(MOVX@DPTR).Inthisapplication,Port2usesstronginternalpul-lupswhenemitting1s.Duringaccessestoexternaldatamemorythatuse8-bitaddresses(MOVX@RI),Port2emitsthecontentsoftheP2SpecialFunctionRegister.Port2alsoreceivesthehigh-orderaddressbitsandsomecontrolsignalsduringFlashprogrammingandverification.Port3Port3isan8-bitbi-directionalI/Oportwithinternalpullups.ThePort3outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort3pins,theyarepull