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(2,1,7)ViterbiFPGA1,1,2(1.100876;2.100083):Vit2erbi,(2,1,7)FPGAViterbi,FPGA,:Viterbi;FPGA;;;:TN74:B:1004-373X(2007)15-090-03FPGAImplementationintheViterbiDecodingSchemeof(2,1,7)ConvolutionalCodeHANKe1,DENGZhongliang1,SHILening2(1.SchoolofElectronicEngineering,BeijingUniversityofPostsandTelecommunications,Beijing,100876,China;2.SchoolofElectronicandInformationEngineering,BeihangUniversity,Beijing,100083,China)Abstract:Convolutionalcodeareuniversallyusedinthenormofmobilecommunicationsystem.ThispaperfirstanalyzestheprincipleofViterbialgorithm,whichistheoptimaldecodingschemeforconvolutionalcodes.ThenthepaperalsopresentstheFPGAimplementationintheViterbidecodingschemeof(2,1,7)convolutionalcode.Themethodgivesthenewbranchweightalgorithmanduniformstateweightmemories,soitcantakeadvantageoftheFPGA.Bythedesignofsurvivalpathex2changeregistermodule,thepowerconsumptionandtheRAMsizeareneededforsavingmetricsaredecreased.Keywords:Viterbidecoding;FPGA;convolutionalcode;RE;TB:2006-12-26,,Viterbi,,,Viterbi1(2,1,7)Viterbi3[1]:ViterbiViterbiViterbi[2](),1(2,1,3),,,,,,(n,k,N),Viterbi(n,k,N),2k(N-1)(),2k2k,k=1,0N-1,2N-1,N,2N,N21(2,1,3)Viterbi,2,,,N2N-1,,,09:(2,1,7)ViterbiFPGA,,,,,,2ViterbiViterbi,2:RE(RegisterExchange)TB(TraceBack)2.1Viterbi,2N-1(),(),,,j(j+2N-2),mn(2j)2j,mo(j)j,:mn(2j)=mo(j)+qj,0mo(j+2N-2)+qj+2N-2,0mn(2j+1)=mo(j)+qj,1mo(j+2N-2)+qj+2N-2,1qj,0=(cj,00r0)+(cj,01r1)qj,1=(cj,10r1)+(cj,11r1)qj,0qj,1j0(0)1,r0r1,cj,xyjxy,,,,?,?,1/2,N,2(N-1)log22(N-1)N=7,42.2(2,1,7)Viterbi,2N-1(64):,,2,,1,()2N=3Vn,V0,A6A5A4A3A2A1,A0,:Vn=A0+V03221,:Vo0=0A5A4A3A2A1Vo1=1A5A4A3A2A1:Vn0=A5A4A3A2A10Vn1=A5A4A3A2A112,(),,(),(2N-1=64),,FPGA,RAM,:Vn0Vo0,Vn1Vo1,,():i-1iA6A5A4A3A2A1]A5A4A3A2A1A6:ii+1A5A4A3A2A1A6]A4A3A2A1A6A5N-1N-1,,,,,i,0(00000b)32(100000b)000000,100000,,i+1,01(00001b)000000,100000,i+2,01000000,100000,01?19200715254þü12.3,,A5A4A3A2A100,L(),:A5A4A3A2A111A6A5A4A3A20(),0;A6A5A4A3A21,1;A5A4A3A2A11A6A5A4A3A20,0;A6A5A4A3A21,1,,,,133,P,:P=(i)mod(L)i(P)Smin,:S1=[(Smin)/2]mod(2N-1)+BP32N-1Sn+1=[(Smin)/2]mod(2N-1)+B(L+P-n)32N-1n=1,2,,L-1;Bv,v=1,2,,L-1,SL-13FPGA,FP2GA,64RAM,FPGAkBSRAM,FPGASRAM,FPGASRAM,,FPGAEAB[3]RAM,,,ACEX1K30EAB6,4(,RAM1)6,40(40,N-157,,RAM2)RAM44:(1),,RAM,,13(2)1,RAMN-1,,0VerilogN-1alwaysN-1,,RAM1:10,32;20,16,32,48;3,4,5,6(3):,RAM10000000100000032,2,,010000000100000,2,,010000000100000,32010000(4)RAM264,RAM2,,,40,(bit),RAM,4,(96)29:(2,1,7)ViterbiFPGA(AMI),:(LMI),,6MVB,,74TCN,IEC61375-1,MVB2,MVBRTP,ARMMVB2,MVB,TCNMVB7[1]TrainCommunicationNetwork(TCN),IEC61375-1,1999.[2]MultifunctionVehicleBusControllerMVBC01DataSheet.[3]NET+50DataSheet.[4],,.MVB[J].,2005(3):19-21,24.[5].ARM[M].:,2003.[6].[M].:,2005.[7].[M].:,2005.,,,,,,,(92)35MHz,120kb/sViterbi,FPGAEABRAM,,,56dB[1]ScllegelC.FundamentalsofDigitalCommunicationandBlockingCoding,Chapter4:ConvolutionalCodes.IEEEPress,2002.[2],.[M].:,2001.[3].Xilinx[M].:,2001.[4],,.FPGAViterbi[J].,2006,29(7):52-54.,1980,,SoC69:ARMMVB2