[主板]主板系统时钟W229B芯片电路图

FrequencyGeneratorforIntegratedCoreLogicwith133-MHzFSBW229BCypressSemiconductorCorporation•3901NorthFirstStreetSanJoseCA95134408-943-2600Document#:38-07223Rev.*ARevisedDecember21,2002Features•MaximizedEMIsuppressionusingCypress’sSpreadSpectrumtechnologyLowjitterandtightlycontrolledclockskewHighlyintegrateddeviceprovidingclocksrequiredforCPU,corelogic,andSDRAMTwocopiesofCPUclockThirteencopiesofSDRAMclockEightcopiesofPCIclockOnecopyofsynchronousAPICclockThreecopiesof66-MHzoutputsTwocopiesof48-MHzoutputsOnecopyofselectable24-or48-MHzclockOnecopyofdoublestrength14.31818-MHzreferenceclockPower-downcontrolSMBusinterfaceforturningoffunusedclocksKeySpecificationsCPU,SDRAMOutputsCycle-to-CycleJitter:.............250psAPIC,48-MHz,3V66,PCIOutputsCycle-to-CycleJitter:...................................................500psCPU,3V66OutputSkew:...........................................175psSDRAM,APIC,48-MHzOutputSkew:.......................250psPCIOutputSkew:.......................................................500psCPUtoSDRAMSkew(@133MHz).......................±0.5nsCPUtoSDRAMSkew(@100MHz).................4.5to5.5nsCPUto3V66Skew(@66MHz)........................7.0to8.0ns3V66toPCISkew(3V66lead)..........................1.5to3.5nsPCItoAPICSkew.....................................................±0.5nsTable1.FrequencySelectionsFS4FS3FS2FS1FS0CPUSDRAM3V66PCIAPICSS0000075.3113.075.337.618.8OFF0000195.095.063.331.615.8–0.6%00010129.0129.086.043.021.5OFF00011150.0113.075.337.618.8OFF00100150.0150.075.037.518.7OFF00101110.0110.073.036.618.3OFF00110140.0140.070.035.017.5OFF00111144.0108.072.036.018.0OFF0100068.3102.568.334.117.0OFF01001105.0105.070.035.017.5OFF01010138.0138.069.034.517.0OFF01011140.0105.070.035.017.5OFF0110066.8100.266.833.416.7±0.45%01101100.2100.266.833.416.7±0.45%01110133.6133.666.833.416.7±0.45%01111133.6100.266.833.416.7±0.45%10000157.3118.078.639.319.6OFF10001160.0120.080.040.020.0OFF10010146.6110.073.336.618.3OFF10011122.091.561.030.515.2–0.6%10100127.0127.084.642.321.1OFF10101122.0122.081.340.620.3–0.6%10110117.0117.078.039.019.5OFF10111114.0114.076.038.019.0OFF1100080.0120.080.040.020.0OFF1100178.0117.078.039.019.5OFF11010166.0124.583.041.520.7OFF11011133.6133.689.044.522.2OFF1110066.6100.066.633.316.6–0.6%11101100.0100.066.633.316.6–0.6%11110133.3133.366.633.316.6–0.6%11111133.3100.066.633.316.6–0.6%BlockDiagramPinConfigurationNote:1.Internalpull-downorpull-upresistorspresentoninputsmarkedwith*or^,respectively.Designshouldnotrelysolelyoninternalpull-uporpull-downresistortosetI/OpinsHIGHorLOW,respectively.[1]VDDQ3VDDQ2PCI1/FS1*XTALPLLREFFREQPLL1X2X1REF2X/FS3*PCI3:748MHz_1/FS4*SI0/24_48MHz#*PLL2OSCVDDQ3I2CSDATALogicSCLK3V66_0:2CPU0:1APICDivider,Delay,andPhaseControlLogic3VDDQ32SDRAM0:1213PWRDWN#PCI0/FS0*PCI2/FS2*/2(FS0:4*)548MHz_0GNDVDDQ3REF2X/FS3*X1X2VDDQ33V66_03V66_13V66_2GNDPCI0/FS0*PCI1/FS1*PCI2/FS2*GNDPCI3PCI4VDDQ3PCI5PCI6PCI7GND48MHz_048MHz_1/FS4*SIO/24_48MHz#*W229BVDDQ2APICGNDVDDQ2CPU0CPU1GNDSDRAM0SDRAM1SDRAM2VDDQ3GNDSDRAM3SDRAM4SDRAM5SDRAM6VDDQ3GNDSDRAM7SDRAM8SDRAM9SDRAM10VDDQ3GND5655545352515049484746454443424140393837363534331234567891011121314151617181920212223242526272832313029VDDQ3SDATAGNDVDD3SDRAM11SDRAM12PWRDWN#^SCLKW229BDocument#:38-07223Rev.*APage2of17IPinDefinitionsPinNamePinNo.PinTypePinDescriptionREF2x/FS3*3I/OReferenceClockwith2xDrive/FrequencySelect3:3.3V14.318-MHzclockout-put.ThispinalsoservesastheselectstraptodeterminedeviceoperatingfrequencyasdescribedinTable1.X14ICrystalInput:Thispinhasdualfunctions.Itcanbeusedasanexternal14.318-MHzcrystalconnectionorasanexternalreferencefrequencyinput.X25ICrystalOutput:Aninputconnectionforanexternal14.318-MHzcrystalconnec-tion.Ifusinganexternalreference,thispinmustbeleftunconnected.PCI0/FS0*11I/OPCIClock0/FrequencySelection0:3.3V33-MHzPCIclockoutputs.ThispinalsoservesastheselectstraptodeterminedeviceoperatingfrequencyasdescribedinTable1.PCI1/FS1*12I/OPCIClock1/FrequencySelection1:3.3V33-MHzPCIclockoutputs.ThispinalsoservesastheselectstraptodeterminedeviceoperatingfrequencyasdescribedinTable1.PCI2/FS2*13I/OPCIClock2/FrequencySelection2:3.3V33-MHzPCIclockoutputs.ThispinalsoservesastheselectstraptodeterminedeviceoperatingfrequencyasdescribedinTable1.PCI3:715,16,18,19,20OPCIClock3through7:3.3V33-MHzPCIclockoutputs.PCI0:7canbeindividuallyturnedoffviaSMBusinterface.3V66_0:27,8,9O66-MHzClockOutput:3.3Voutputclocks.TheoperatingfrequencyiscontrolledbyFS0:4(seeTable1).48MHz_022O48-MHzClockOutput:3.3Vfixed48-MHz,non-spreadspectrumclockoutput.48MHz_1/FS4*23I/O48-MHzClockOutput/FrequencySelection4:3.3Vfixed48-MHz,non-spreadspectrumclockoutput.ThispinalsoservesastheselectstraptodeterminedeviceoperatingfrequencyasdescribedinTable1.SIO/24_48MHz#*24I/OClockOutputforSuperI/O:ThisistheinputclockforaSuperI/O(SIO)device.Duringpowerup,italsoservesasaselectionstrap.IfitissampledHIGH,theoutputfrequencyforSIOis24MHz.IftheinputissampledLOW,theoutputis48MHz.PWRDWN#30IPowerDownControl:LVTTL-compatibleinputthatplacesthedeviceinpower-downmodewhenheldLOW.CPU0: