CY7C4225V中文资料

64/256/512/1K/2K/4Kx18Low-VoltageSynchronousFIFOsCY7C4225V/4205V/4215VCY7C4425V/4235V/4245VCypressSemiconductorCorporation•198ChampionCourt•SanJose,CA95134-1709•408-943-2600Document#:38-06029Rev.*CRevisedSeptember7,2005Features•3.3Voperationforlowpowerconsumptionandeasyintegrationintolow-voltagesystems•High-speed,low-power,first-infirst-out(FIFO)memories•64x18(CY7C4425V)•256x18(CY7C4205V)•512x18(CY7C4215V)•1Kx18(CY7C4225V)•2Kx18(CY7C4235V)•4Kx18(CY7C4245V)•0.65µCMOS•High-speed67-MHzoperation(15-nsread/writecycletimes)•Lowpower—ICC=30mA•5Vtolerantinputs(VIHMAX=5V)•Fullyasynchronousandsimultaneousreadandwriteoperation•Empty,Full,HalfFull,andprogrammableAlmostEmptyandAlmostFullstatusflags•TTL-compatible•Retransmitfunction•OutputEnable(OE)pin•Independentreadandwriteenablepins•Supportsfree-running50%dutycycleclockinputs•Width-ExpansionCapability•Depth-ExpansionCapability•64-pin14×14TQFPand64-pin10×10STQFP•Pb-FreepackagesavailableFunctionalDescriptionTheCY7C42X5Varehigh-speed,low-power,first-infirst-out(FIFO)memorieswithclockedreadandwriteinterfaces.Allare18bitswide.TheCY7C42X5VcanbecascadedtoincreaseFIFOdepth.ProgrammablefeaturesincludeAlmostFull/AlmostEmptyflags.TheseFIFOsprovidesolutionsforawidevarietyofdatabufferingneeds,includinghigh-speeddataacquisition,multiprocessorinterfaces,andcommunicationsbuffering.TheseFIFOshave18-bitinputandoutputportsthatarecontrolledbyseparateclockandenablesignals.TheinputportiscontrolledbyaFree-RunningClock(WCLK)andaWriteEnablepin(WEN).WhenWENisasserted,dataiswrittenintotheFIFOontherisingedgeoftheWCLKsignal.WhileWENisheldactive,dataiscontinuallywrittenintotheFIFOoneachcycle.TheoutputportiscontrolledinasimilarmannerbyaFree-RunningReadClock(RCLK)andaReadEnablepin(REN).Inaddition,theCY7C42X5VhaveanOutputEnablepin(OE).Thereadandwriteclocksmaybetiedtogetherforsingle-clockoperationorthetwoclocksmayberunindependentlyforasynchronousread/writeapplications.Clockfrequenciesupto66MHzareachievable.RetransmitandSynchronousAlmostFull/AlmostEmptyflagfeaturesareavailableonthesedevices.DepthexpansionispossibleusingtheCascadeInput(WXI,RXI),CascadeOutput(WXO,RXO),andFirstLoad(FL)pins.TheWXOandRXOpinsareconnectedtotheWXIandRXIpinsofthenextdevice,andtheWXOandRXOpinsofthelastdeviceshouldbeconnectedtotheWXIandRXIpinsofthefirstdevice.TheFLpinofthefirstdeviceistiedtoVSSandtheFLpinofalltheremainingdevicesshouldbetiedtoVCC.TheCY7C42X5Vprovidesfivestatuspins.Thesepinsaredecodedtodetermineoneoffivestates:Empty,AlmostEmpty,HalfFull,AlmostFull,andFull(seeTable2).TheHalfFullflagsharestheWXOpin.Thisflagisvalidinthestand-aloneandwidth-expansionconfigurations.Inthedepthexpansion,thispinprovidestheexpansionout(WXO)informationthatisusedtosignalthenextFIFOwhenitwillbeactivated.TheEmptyandFullflagsaresynchronous,i.e.,theychangestaterelativetoeithertheReadClock(RCLK)orthewriteclock(WCLK).WhenenteringorexitingtheEmptystates,theflagisupdatedexclusivelybytheRCLK.TheflagdenotingFullstatesisupdatedexclusivelybyWCLK.Thesynchronousflagarchitectureguaranteesthattheflagswillremainvalidfromoneclockcycletothenext.Asmentionedpreviously,theAlmostEmpty/AlmostFullflagsbecomesynchronousiftheVCC/SMODEistiedtoVSS.Allconfigurationsarefabricatedusinganadvanced0.65µP-WellCMOStechnology.InputESDprotectionisgreaterthan2001V,andlatch-upispreventedbytheuseofguardrings.CY7C4425V/4205V/4215VCY7C4225V/4235V/4245V64/256/512/1K/2K/4Kx18Low-VoltageSynchronousFIFOsCY7C4225V/4205V/4215VCY7C4425V/4235V/4245VDocument#:38-06029Rev.*CPage2of20LogicBlockDiagramTHREE–STATEOUTPUTREGISTERREADCONTROLFLAGLOGICWRITECONTROLWRITEPOINTERREADPOINTERRESETLOGICEXPANSIONLOGICINPUTREGISTERFLAGPROGRAMREGISTERRENRCLKFFEFPAEQ0–17WENWCLKRSFL/RTWXIOERAMARRAY64x18256x18512x181Kx182Kx184Kx18PAFWXO/HFRXIRXOSMODED0–17PinConfigurationEFSTQFP/TQFPTopView12345678910111213141548474645444342414039383736353433176418631962206121602259235824572556265527542853295230513150324916D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0D15Q15GNDQ16Q17GNDVCCRSOELDRENRCLKGNDD17D16PAEWCLKWENWXIVCCPAFRXIFFWXO/HFRXOQ0Q1GNDQ2Q3Q14Q13GNDQ12Q11VCCQ10Q9GNDQ8Q7Q6Q5GNDQ4VCCVCC/SMODEFL/RTCY7C4425VCY7C4205VCY7C4215VCY7C4225VCY7C4235VCY7C4245VCY7C4225V/4205V/4215VCY7C4425V/4235V/4245VDocument#:38-06029Rev.*CPage3of20SelectionGuideCY7C42X5V-15CY7C42X5V-25CY7C42X5V-35UnitMaximumFrequency66.74028.6MHzMaximumAccessTime111520nsMinimumCycleTime152535nsMinimumDataorEnableSet-up467nsMinimumDataorEnableHold112nsMaximumFlagDelay111520nsOperatingCurrentCommercial303030mACY7C4425VCY7C4205VCY7C4215VCY7C4225VCY7C4235VCY7C4245VDensity64x18256x18512x181Kx182Kx184Kx18Packages64-pin14x14TQFP64-pin10x10STQFP64-pin14x14TQFP64-pin10x10STQFP64-pin14x14TQFP64-pin10x10STQFP64-pin14x14TQFP64-pin10x10STQFP64-pin14x14TQFP64-pin10x10STQFP64-pin14x14TQFP64-pin10x10STQFPPinDefinitionsSignalNameDescriptionI/OFunctionD0−17DataInputsIDatainputsforan18-bitbus.Q0−17DataOutputsODataoutputsforan18-bitbus.WENWriteEnableIEnablestheWCLKinput.RENReadEnableIEnablestheRCLKinput.WCLKWriteClockITherisingedgeclocksdataintotheFIFOwhenWENisLOWandtheFIFOisnotFull.WhenLDisass