多模视频解码芯片中帧内预测模块的设计与实现

上海交通大学硕士学位论文多模视频解码芯片中帧内预测模块的设计与实现姓名：徐张磊申请学位级别：硕士专业：通信与信息系统指导教师：郑世宝20080101IH.264ITU-TISO/IEC,AVSMPEG2MPEG2MPEG2H.264AVSH.264AVSH.264AVSMPEG-2H.264AVSIIH.264AVSSOCVLDH.264FRExt8×816×168×16VerilogHDLRTLC150MHzH.264AVSIIIDESIGNANDIMPLEMENTATIONOFINTRAPREDICTIONMODULEFORMULTI-STANDARDDECODERCHIPABSTRACTH.264/AVCisanewvideocodinginternationalstandardproposedbyJointVideoTeam(JVT),whichisorganizedbytheITU-TVideoCodingExpertsGroup(VCEG)andtheISO/IECMovingPictureExpertsGroup(MPEG),havinghighperformanceonvideocodec,AVSisChinesedigitalaudio/videocodingstandardwithindependentintellectualproperty,MPEG2hasbeenwidelyusednowadays.BothH.264andAVSarehotproblemsinrecentimagecommunicationresearcharea,andtherangeMPEG2hasinfluenceoncannotbenegected.Duetoincreasinglymulti-standardvideocodecsolutionproposedinthemultimediamarket,itisnecessarytocombinethesestandardsinonedecoderchip.Thesestandardsalladoptedtheblock-basedmixcodingstructure,havingsimilaritiesamongtheirsystemarchitecture,whichmakesthedevelopmentofdecoderchipsupportingmanstandardsfeasible.AmongMPEG2,H.264andAVS,onlyH.264andAVSposesstheintra-predictionmodule.Inthisthesis,aVLSIIVarchithecureofintra-predictionmodulesupportingH.264andAVSisproposed.Firstofall,thisthesisintroducestheprincipleofvideocompressing,looksbackonthehistoryofdevelopmentofvideocodingstandards,introducesmain-streamstandardsMPEG2,H.264andAVS,andtaksalookontheexistingvideodecodingchip,andthedesignflowofchip;also,thefirstpartpresentstheaimandfocusofthisthesis.Then,thisthesisexpatiatesthebasicprincipleofpredictioncoding,summarizesthedevelopmentofintra-predictiontechnology,andresearchedonH.264andAVSintra-predictionintermsofalgorithm.Theresearchonalgorithmisthetheorybaseofmoduledesigninthenextstep.BasedontheanalysisofvideodecodingSOCsystem,thisthesisdesignstheintra-predictionmoduleindetail,includingtheinterfacebetweenmoduleandbus,predictionmodedecisionmoduleandthemostimportantpredictioncalculationunit.Designofeverymoduleisbasedonalgorithm,throughtheanalysisofdifferencesandsimilaritiesoftwostandards.Reconfigurablecalculationunitisdsignedinordertoimprovetheshareofhardwareresources.Thisthesisproposesahardwarearchitecturethatcansupportallintra-predictionalgorithmsincluding8×8Luma,16×16and8×16Chromamacroblock.VThisthesisimplementstheintra-predictoinmodulusingVerilogHDL,andfinishsthefunctionsimulation.ThecorrectnessofthedesignisprovedbythecomparisionbetweenthehardwareandCreferencemodel.ThisthesisalsosynthesizesthemoduleandgettheresourceittakenonFPGAandthefrequency.Theresultsshowsthatthefrequencycanreach150MHz,meetingtherequirementofhighdefinitionrealtimedecoding.KEYWORDS:H.264AVSDecoderChipIntraPredictionMulti-standardHardwareArchitectureVIII1-1..........................................................................................................21-2H.264..............................................................................................................32-1DC.............................................................................................112-24×4....................................................................132-34×48............................................................................142-44×4................................................................................................142-516×16...........................................................................................................162-6...............................................................................................172-7AVS...........................................................................................................193-1...........................................................................................223-2SOC....................................................................................................................243-3VideoDecoder............................................................................................253-4.......................................................................................273-5...........................................................................................................283-6...................................................................................................................353-7...............................................................................................................363-8H.264............................................................................................373-9AVS................................................................................................373-10.........................................................................................373-1116x16.....................................................................393-124x48x8..............................................................................403-13PlaneA......................................................................463-14HV.................................................................