VHDL与数字集成电路设计VHDL7-1

2CombinationalLogicR1R2CinCoutOutInCLK3DClkQDQClktc-qtholdPWmtsutd-qDelayscanbedifferentforrisingandfallingdatatransitionsT4DClkQDQClktc-qtholdTtsuDelayscanbedifferentforrisingandfallingdatatransitions5243PowerSupplyInterconnect5Temperature6CapacitiveLoad7CouplingtoAdjacentLines1ClockGenerationDevicesSourcesofclockuncertainty6Clockskew◦Spatialvariationintemporallyequivalentclockedges;deterministic+random,tSKClockjitter◦Temporalvariationsinconsecutiveedgesoftheclocksignal;modulation+randomnoise◦Cycle-to-cycle(short-term)tJS◦LongtermtJLVariationofthepulsewidth◦Importantforlevelsensitiveclocking7BothskewandjitteraffecttheeffectivecycletimeOnlyskewaffectstheracemarginClkClktSKtJS8R1In(a)PositiveskewCombinationalLogicDQtCLK1CLKdelaytCLK2R2DQCombinationalLogictCLK3R3???DQdelayR1In(b)NegativeskewCombinationalLogicDQtCLK1delaytCLK2R2DQCombinationalLogictCLK3R3???DQdelayCLK9CLK1CLK2TCLKdTCLK+d+thd2143Launchingedgearrivesbeforethereceivingedge10CLK1CLK2TCLKdTCLK+d2143Receivingedgearrivesbeforethelaunchingedge11R1DQCombinationalLogicInCLKtCLK1R2DQtCLK2tc-qtc-q,cdtsu,tholdtlogictlogic,cdMinimumcycletime:T-=tc-q+tsu+tlogicWorstcaseiswhenreceivingedgearrivesearly(positive)12R1DQCombinationalLogicInCLKtCLK1R2DQtCLK2tc-qtc-q,cdtsu,tholdtlogictlogic,cdHoldtimeconstraint:t(c-q,cd)+t(logic,cd)thold+WorstcaseiswhenreceivingedgearriveslateRacebetweendataandclock13CLK-tjitterTCLKtjitterCLKInCombinationalLogictc-q,tc-q,cdtlogictlogic,cdtsu,tholdREGStjitter14ClkTTSUTClk-QTLMLatestpointoflaunchingEarliestarrivalofnextcycleTJI+15Iflaunchingedgeislateandreceivingedgeisearly,thedatawillnotbetoolateif:MinimumcycletimeisdeterminedbythemaximumdelaysthroughthelogicTc-q+TLM+TSUT–TJI,1–TJI,2-Tc-q+TLM+TSU++2TJITSkewcanbeeitherpositiveornegative16ClkTClk-QTLmEarliestpointoflaunchingDatamustnotarrivebeforethistimeClkTHNominalclockedge17MinimumlogicdelayIflaunchingedgeisearlyandreceivingedgeislate:Tc-q+TLM–TJI,1TH+TJI,2+Tc-q+TLMTH+2TJI+18CLKClockisdistributedinatree-likefashionH-tree19[Restle98]20DriverDriverDriverDriverGCLKGCLKGCLKGCLK•Norc-matching•Largepower212phasesinglewireclock,distributedglobally2distributeddriverchannels◦ReducedRCdelay/skew◦Improvedthermaldistribution◦3.75nFclockload◦58cmfinaldriverwidthLocalinvertersforlatchingConditionalclocksincachestoreducepowerMorecomplexracecheckingDevicevariationtrise=0.35nstskew=150pstcycle=3.3nsClockwaveformLocationofclockdriverondiepre-driverfinaldrivers22ClockDrivers23242Phase,withmultipleconditionalbufferedclocks◦2.8nFclockload◦40cmfinaldriverwidthLocalclockscanbegated“off”tosavepowerReducedload/skewReducedthermalissuesMultipleclockscomplicateracecheckingtrise=0.35nstskew=50pstcycle=1.67nsEV6(Alpha21264)Clocking600MHz–0.35micronCMOSGlobalclockwaveformPLL25Intpd,regtpd1DR1QCLKLogicBlock#1tpd2DR2QLogicBlock#2tpd3DR3QDR4QLogicBlock#326R2OutF2IntpF2StartDoneR1F1tpF1StartDoneR3F3tpF3StartDoneReqReqReqReqAckAckAckACKHSHSHS27TwoPhaseHandshake28ABFn+10011010(b)Truthtable(a)Schematic10FnFn1FABCSFFRQAB(a)Logic(b)MajorityFunction(c)DynamicABBBAVDDBFABVDDVDD2930CCR1InOutEnAckiReqiR2R3CReq0AckoDone31DigitalSystemDividerCrystalOscillatorPLLChip1DigitalSystemPLLChip2fsystem=Nxfcrystalfcrystal,200MhzDataClockBufferreferenceclock32PhasedetectorChargepumpDividebyNLoopfilterVCOReferenceclockLocalclockSystemClockUpDownvcont33OutputbeforefilteringTransfercharacteristic34(c)Timingwaveforms(a)schematic(b)statetransitiondiagramABUPDNABUPDNDQDQABRstRstUPDNUP=0DN=1UP=0DN=0UP=1DN=0BBAAAB35ABUPDN36VDDUPDNToVCOControlInput3738PDCPVCO÷NPhase-LockedLoop(VCO-Based)UDfOfREFFilter39VCDLCP/LFPhaseDetectorVCDLCP/LFPhaseDetectorDigitalCircuit晻?DigitalCircuit晻?GLOBALCLK