Verilog HDL数字设计与综合 夏宇闻译(第二版)课后题答案

第二章/*1----------------------------------------------*/moduleIS;//...SCsc1;MEMmem1;Xbarxbar1;endmodule;moduleSC;//...endmodule;moduleXbar;//...endmodule;moduleMEM;//...endmodule;moduleTop;ISis1;endmodule/*2----------------------------------------------*/moduleFA;endmodulemoduleRipple_Add;FAfa0;FAfa1;FAfa2;FAfa3;Endmodule第三章/*1---------------------------------------------------------------*/a:8b0111_1011b:16hxxxxc:-2(1010)--取反（1101）----再加一（1110）d:'h1234/*2---------------------------------------------------------------*/a:正确b:正确c:正确d:正确/*3---------------------------------------------------------------*/a：合法b：合法c：不合法，含有$为延时含义d：标识符组成：字母数字下划线。/*4---------------------------------------------------------------*/a:wire[7:0]a_in;b:reg[31:0]c:integercount;d:timesnap_shot;e:integerdelays[20];f:reg[63:0]mem[256];g:parametercach_size=256;/*5---------------------------------------------------------------*/a:1010b:10c:400第四章/*1-----------------------------------------------------------------------*///模块的基本组成部分有哪些？哪几个部分必须出现？模块定义已关键字module开始，模块名，端口列表，端口声明和可选的参数声明出现在其他部分的前面，endmodule必须为最后一条语句1）wire。reg和其他类型的变量的声明2）数据流语句（assign，连续赋值语句）3）低层模块实例4）always和initial块，所有的行为语句都在这些块中5)任务和函数。其中module和模块名和endmodule是必不可少的。/*2-----------------------------------------------------------------------*///一个不与外界环境交互的模块是否有端口？模块定义中是否有端口列表？不与外界交互即没有端口列表，在没有端口的情况下端口列表也是不存在的。/*3-----------------------------------------------------------------------*/moduleshift_reg(reg_in[3:0],clock,reg_out[3:0]);input[3:0]reg_in;inputclock;output[3:0]reg_out;//......endmodule;/*4-----------------------------------------------------------------------*///connectinordermodulestimulus();reg[3:0]REG_IN;wire[3:0]REG_OUT;regCLK;shift_regsr1(REG_IN,CLK,REG_OUT);endmodule/*5-----------------------------------------------------------------------*///connectbynamemodulestimulus();reg[3:0]REG_IN;wire[3:0]REG_OUT;regCLK;shift_regsr1(.clock(CLK),.reg_in(REG_IN),.reg_out(REG_OUT));endmodule/*6-----------------------------------------------------------------------*/stimulus.REG_INstimulus.CLK;stimulus.REG_OUT;/*7-----------------------------------------------------------------------*/stimulus.sr1;stimulus.sr1.clock;stimulus.sr1.reg_in;stimulus.sr1.reg_out;第五章/*1--------------------------------------------------------------------*///利用双输入的nand门设计自己的与或非门。//my_andmodulemy_and(out,in1,in2);inputin1,in2;outputout;endmodule//my_notmodulemy_not(out,in1);inputin1;outputout;nand(out,in1,in1);endmodule//my_andmodulemy_or(out,in1,in2);wiret;nand(t,in1,in2);nand(out,t,t);//endmodule/*2--------------------------------------------------------------------*///使用上题中完成的my_or，my_and，my_not构造一个双//输入的xor门，其功能是计算z=x'y+xy'/*3--------------------------------------------------------------------*///全加器modulesum(a,b,c_in,sum,c_out);inputa,b,c_in;outputsum,c_out;wirey1,y2,y3,y4;wirex1,x2,x3;or(sum,y1,y2,y3,y4);and(y1,a,b,c_in);and(y2,x1,b,x3);and(y3,x1,x2,c_in);and(y4,a,x2,x3);not(x1,a);not(x2,b);not(x3,c);wirej1,j2,j3;or(c_out,j1,j2,j3);and(j1,a,b);and(j2,b,c_in);and(j3,a,c_in);endmodule/*4--------------------------------------------------------------------*///带有延时的SR锁存器moduleSR(reset,q,set,qbar);inputreset,set;outputq,qbar;wireline1,line2;nor(line2,reset,line1);nor(line1,set,line2);endmodule/*---------------------------ISE中一个端口如何接多根线?????????????????????*//*5--------------------------------------------------------------------*/moduleselect(out,in1,in2,s);inputin1,in2,s;outputout;//3为上升延迟，4为下降延时，5为关断延迟。bufif1#(1:2:3,3:4:5,5:6:7)b2(out,in1,s);bufif0#(1:2:3,3:4:5,5:6:7)b1(out,in2,s);endmodule/*--------------------------------------------------------------------*/第六章/*1----------------------------------------------------------------*///全减器//输入:x,y,z(前面的借位)//输出：差和借位modulesub(x,y,z,D,B);inputx,y,z;outputD,B;wirey0,y1,y2,y3;wirej1,j2,j0;//非门not(j0,x);not(j1,y);not(j2,z);and(y0,j0,j1,j2);and(y1,j0,y,j2);and(y2,x,j1,j2);and(y3,x,y,z);or(D,y0,y1,y2,y3);//Bwirea1,a0,a2;and(a0,j0,y);and(a1,j0,z);and(a2,y,z);or(B,a1,a0,a2);endmodule//激励模块：modulestimulus;//initial从仿真0时刻开始，而且只执行一次，若程序中有若干个initial块，则并发执行。rega,b,c;wired,e;regi;subsub(a,b,c,d,e);initialfor(i=1;i0;)begin#5;a=1;b=1;c=0;#5;a=1;b=0;c=0;endendmodule/*2----------------------------------------------------------------*///大小比较器modulecmp(A,B,A_gt_B,A_lt_B,A_eq_B);input[3:0]A,[3:0]B;outputA_gt_B,A_lt_B,A_eq_B;endmodule/*3----------------------------------------------------------------*/modulesyn_counter(clear,clock,count_enable,Q);inputclear,clock,count_enable;output[3:0]Q;wire[3:0]Q;wireb1,b2,b3;nand(b1,count_enable,Q[1]);nand(b2,b1,Q[2]);nand(b3,b2,Q[3]);jkjk1(count_enable,count_enable,clear,clock,Q[0],);jkjk2(b1,b1,clear,clock,Q[1],);jkjk3(b2,b2,clear,clock,Q[2],);jkjk4(b3,b3,clear,clock,Q[3],);endmodulemodulejk(J,K,clear,clock,q,qbar);inputJ,K,clear,clock;outputq,qbar;wirea,y,c,b,ybar,cbar,d;not(cbar,clock);nanda1(a,qbar,J,clock,clear);nanda2(b,clock,K,q);nanda3(y,a,ybar);nanda4(ybar,y,clear,b);nanda5(c,y,cbar);nanda6(d,cbar,ybar);nanda7(q,c,qbar);nanda8(qbar,q,clea