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1of157093002Note:Somerevisionsofthisdevicemayincorporatedeviationsfrompublishedspecificationsknownaserrata.Multiplerevisionsofanydevicemaybesimultaneouslyavailablethroughvarioussaleschannels.Forinformationaboutdeviceerrata,clickhere:(FDL)messagesinthereceiveandtransmitpaths,collectlineperformancedata,andperformbasicchannelconditioningandmaintenance.TheDS2196containsallofthenecessaryfunctionsforconnectiontoT1lineswhethertheyareDS1longhaulorDSX–1shorthaul.TheclockrecoverycircuitryautomaticallyadjuststoT1linesfrom0fttoover6000ftinlength.ThedevicecangeneratebothDSX–1linebuildoutsaswellasCSUlinebuildoutsof-7.5dB,-15dB,and-22.5dB.Theon-boardjitterattenuator(selectabletoeither32bitsor128bits)canbeplacedineitherthetransmitorreceivedatapaths.Theframerlocatestheframeandmultiframeboundariesandmonitorsthedatastreamforalarms.Thedevicecontainsasetofinternalregistersthattheusercanaccessandusetocontroltheunit’soperationoftheunit.QuickaccessthroughtheparallelcontrolportallowsasinglecontrollertohandlemanyT1lines.ThedevicefullymeetsallofthelatestT1specifications.PACKAGEOUTLINEFEATURES§Twofull-featuredframersandashort/long-haullineinterfaceunit(LIU)inonesmallpackage§BasedonDallasSemiconductor’ssingle-chiptransceiver(SCT)family§TwoHDLCcontrollerswith64-bytebuffersthatcanbeusedfortheFDLorDS0channels§SupportsNPRMsandSPRMsasperANSIT1.403-1998§Canbecombinedwithashort/long-haulLIUoraHDSLmodemchipsettocreatealow-costofficerepeater/NIU/CSU,oraHDSL1/HDSL2terminalunitwithenhancedmonitoringanddatalinkcontrol§SupportsfractionalT1§CanconvertfromD4toESFframingandESFtoD4framing§32-bitor128-bitcrystal-lessjitterattenuator§Cangenerateanddetectrepeatingin-bandpatternsfrom1to8bitsor16bitsinlength§DetectsandgeneratesRAI-CIandAIS-CI§GeneratesDS1idlecodes§On-chipprogrammableBERTgeneratoranddetector§Allkeysignalsareroutedtopinstosupportnumeroushardwareconfigurations§SupportsbothNRZandbipolarinterfaces§CancreateerrorsintheF-bitpositionandBERTinterfacedatapaths§8-bitparallelcontrolportthatcanbeuseddirectlyoneithermultiplexedornonmultiplexedbuses(IntelorMotorola)§IEEE1149.1JTAGBoundaryScan§3.3Vsupplywith5Vtolerantinputsandoutputs§100-pinLQFP(14mmx14mm)packageORDERINGINFORMATIONPARTTEMPRANGEPIN-PACKAGEDS2196L0ºCto+70ºC100LQFPDS2196LN-40ºCto+85ºC100LQFP–CHANNELCODE(IDLE)GENERATIONANDLOOPBACK.....................................7211.1TRANSMITSIDECODEGENERATION..................................................................................7211.2RECEIVESIDECODEGENERATION......................................................................................7312PROGRAMMABLEIN–BANDCODEGENERATIONANDDETECTION.........................7413CLOCKBLOCKINGREGISTERS..............................................................................................8314TRANSMITTRANSPARENCY....................................................................................................8515BERTFUNCTION..........................................................................................................................8615.1B