逻辑综合synthesis(测试版)

哈理工大学软件学院集成系共享文档，严禁翻版2012.7.3综合复习资料（综合测试版）一、名词解释1、Synthesis:synthesisisthetransformationofanideaintoamanufacturabledevicetocarryoutanintendedfunction.2、SOLD(SynopsysOn-LineDocumentation):Itisawebsitetoprovideanswers.3、STA(StaticTimingAnalysis):Amethodfordeterminingofacircuitmeetstimingconstraintswithouthavingtosimulateclockcycles.4、Clockskew:Toaccountforvaryingdelaysbetweentheclocknetworkbranches.5、Jitter:Becausesomeuncertainfactors,whichleadstotheclockhappendrift.6、RTL(RegisterTransferLevel):Itisacodingstylemeansdescribingtheregisterarchitecture,thecircuittopology,andthefunctionalitybetweenregisters.7、TCL(ToolCommandLanguage):Itisan“open”,industry-standardlanguage,developedatUCABerkeley.8、PVT:STAscaleseachcellandnetdelaybasedonProcess,Voltage,andTemperaturevariations.9、CTS(ClockTreeSynthesis):Bufferclocktimingdeviceintherightplace,andavoidtheCLOCKtoSKEW.10、BDD(BinaryDecisionDiagram):ThebinarydecisiondiagramisusedtorepresentthedatastructureoftheBooleanfunctions.二、填空1、Designobjects:Design、Cell、Reference、Port、Pin、Net、Clock2、Theadvantagesofsynthesis:reusability、verifiable、portability、prestige、productivity、abstraction、designtricks3、SynthesisisConstraint-Driven,isPath-Based.4、Synthesis=translation+optimization+mapping5、GTECHhasnothingtodowithtechnology.三、简答1、Cell-BaBehavioralLevel答：1.Behaviorallevel2.RTLLevel3.LogicSynthesis4.LogicLevelDesign5.CircuitLevelDesign6.LayoutLevelDesign7.PostVerificationsed-Flow2、LogicSynthesisOverview答：1.RTLDesign2.HDLCompiler3.DesignCompiler4.OptimizedGate-levelNetlist3、What.synopsys_dc.setupdefined答：link_librarytarget_librarysymbol_library哈理工大学软件学院集成系共享文档，严禁翻版2012.7.3search_pathsynthetic_library4、whatis.synopsys_dc.setup？答：启动文件（startupfiles）DC:.synopsys_dc.setupDefinedprocesspathtothelibraryandtheotherforthelogicsynthesisparameters.定义工艺库的路径和其他用于逻辑综合的参数。ThreedistinctfilesarereadandexecutedwhenDCisinvoked1st.system-wide(donotmodify):(e.g.$SYNOPSYS/admin/setup/)2nd.User’shomedirectory(e.g.~ccyang/)3rd.User’scurrentworkingdirectory(e.g.~ccyang/dc/)5、StaticTimingAnalysis(DesignTime)答：Amethodfordeterminingifacircuitmeetstimingconstraintswithouthavingtosimulateclockcycles.1.Designsarebrokendownintosetsoftimingpaths2．Thedelayofeachpathiscalculated3.Allpathdelaysarecheckedtoseeiftimingconstraintshavebeenmet6、TimingGroupsHowtoorganizetimingpathsintogroup?答：7、TimingPathExercise答：Howmanytimingpathsdoyousee?11Howmanypathgroupsarethere?38、HDLCodingStyleforSynthesis答：1.SynthesizableVerilogHDL2.SometricksinVerilogHDL3.Designwarelibrary哈理工大学软件学院集成系共享文档，严禁翻版2012.7.39、DesignConstraintsSetting答：1.SettingDesignEnvironment2.SettingDesignConstraint10、operatingenvironment答：Theoperatingenvironmentaffectsthecomponentsselectedfromtargetlibraryandtimingthroughyourdesign.11、OperatingCondition/InputDriveImpedance12、WireLoadModel答：1.Wireloadmodelestimateswirecapaonchiparea&cellfanout.2.Settingthisinformationduringcompmodelthedesignmoreaccurately.13、SequentialCircuit-SpecifyClock答：1.Selectclockport2.Attributes/Clocks/Specifycreate_clock:defineyourclock’swaveform&respecttheset-uptimerequirementsofallclockedflip-flopsdc_shellcreate_clock“clk”-period50-waveform{025}哈理工大学软件学院集成系共享文档，严禁翻版2012.7.3set_fix_hold:respecttheholdtimerequirementofallclockedflip-flopsdc_shellset_fix_holdclkset_dont_touch_network:donotre-buffertheclocknetworkdc_shellset_dont_touch_networkclk14、groupFSM答：TogroupFSM,usethefollowingdc_shellcommanddc_shellset_fsm_state_vector{present_State[2],present_State[1],present_State[0]}dc_shellgroup-fsm-design_namefsm_name15、WhatisSetupTimeandHoldTime?答：SetupTime:Thelengthoftimethatdatamuststabilizebeforetheclocktransition.Themaximumdatapathisusedtodetermineifsetupconstraintismet.HoldTime:Thelengthoftimethatdatamustremainstableattheinputpinaftertheactiveclocktransition.Theminimumdatapathisusedtodetermineifholdtimeismet.16、Whatisthenameoflibraryandwhatarethefunctionsoflibrary?哈理工大学软件学院集成系共享文档，严禁翻版2012.7.3答：1.Link_library:thelibraryusedforinterpretinginputdescription.2.Target_library:theASICtechnologythatthedesignismappedto.3.Symbol_library:usedduringschematicgeneration.4.Synthetic_library:designwarelibrarytobeused.17、Whypartitionadesign?答：Partitioningisdrivenbymany(oftencompeting)needs:1.Separatedistinctfunctions.2.Achieveworkablesizeandcomplexity.3.Manageprojectinteamenvironment.4.Designreuse.5.Meetphysicalconstraints.18、HowtoPartitioning？19、Howtoconstraint？答：set_max_area100create_clock–period10[get_portsclk]set_dont_touch_network[get_clocksclk]set_input_delay–max4–clockclk[get_portsA]set_output_delay–max5.4–clockclk[get_portB]20、Timingpath答：DesignTimebreaksdesignsintosetsofsignalpaths,eachpathhasastartpointandanendpoint.哈理工大学软件学院集成系共享文档，严禁翻版2012.7.3Startpoints:inputportsclockpinsofsequentialdevicesEndpoints:outputportsdatainputspinsofsequentialdevice21、Set_driving_cellandSet_load答：Set_driving_cellallowstheusertospecifyarealisticexternalcelldrivingtheinputports.syntax：set_driving_cell–lib_celland2a0\[get_portsIN1]Set_loadallowstheusertospecifytheexternalcapacitiveloadonports.syntax:set_load5[get_portsOU