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25220082MECHANICAL&ELECTRICALENGINEERINGMAGAZINEVol.25No.2Feb.2008:2007-08-15:(1979-),,,VHDLCPLDPWM,,(,310014):(VHDL)(CPLD)PWM,PWM,,:;;:TP216:A:1001-4551(2008)02-0093-04APWMgeneratorbasedonVHDLandCPLDLINWang2jian,FENGHao,HUALiang(CollegeofInformationEngineering,ZhejiangUniversityofTechnology,Hangzhou310014,China)Abstract:ThedesignofPWMgeneratorbasedonVHDLandCPLDwasintroduced.ThetwopositiveandnegativephasePWMwaveout2signalswereproduced,thetwoout2signalslockedeachotherandlogicdelaywererealized.Thegeneratorisdesignedwiththedigital,ithassimplestructure,accuratecontrolandcanbeprogrammingonline.Keywords:VHSIChardwarelanguage(VHDL);complexprogrammablelogicdevicedescriptionlanguage(CPLD);plusewidthmodulation(PWM)generator0,PWM[1,2]CPLDPWM,AlteraMAX7000CPLD(EPM7128SLC84215[3])PWMAT89S51PWM,CPLD;CPLD,D/A,PWMCPLD/FPGAPWM,[4,5][6,7],CPLDEABLPM_ROM,PWMCPLDPWM1PWMPWMPWM6PWM,1CPLD40M,20M20M,overflow,T,PWM,12,PWM20MHz/212=4.8828125kHzPWM,PWMclken2updown3PWM,PWMPWM,DEADZONE(tffout),8,120106256=12.8us,12.8us11PWM2AlteraMAX+PLUSIIVHDL2.1,22VHDL:entitycounterisport(clk:instd_logic;overflow:outstd_logic;countq:outstd_logic_vector(11downto0));endcounter;architecturebehaveofcounterissignalcountq_temp:std_logic_vector(11downto0);beginprocess(clk)beginifclkeventandclk=1thenifcountq_temp111111111111thenoverflow=0;countq_temp=countq_temp+1;elseoverflow=1;countq_temp=000000000000;endif;elsenull;endif;endprocess;countq=countq_temp;endbehave;2.2,33,COUNTQPWMCOUNTQ,T,PWMT0,PWM:1=countq212,2=212-countq212(1)EN2,I/O,EN2,COUNTQ,PWMEN2,CLKUPDOWN,CLKUPDOWNI/O,UPDOWN,UPDOWN,CLK,COUNTQ1;UPDOWN,CLK,COUNTQ1CPLDCOUNTQPWMVHDL:entityfixcounterisport(clk:instd_logic;en2:instd_logic;updown:instd_logic;countq:outstd_logic_vector(11downto0));endfixcounter;architecturebehaveoffixcounterissignalcountq_temp:std_logic_vector(11downto0);beginprocess(clk,en2)beginifclkeventandclk=1thenifen2=0thenifupdown=1thencountq_temp=countq_temp-1;elsifupdown=0thencountq_temp=countq_temp-1;elsenull;endif;elsifen2=1thencountq_temp=100000000000;elsenull;endif;endif;endprocess;4925countq=countq_temp;endbehave;2.3CPLDEABLPM_ROM,T,44LPM_COMPARECLKUSEDaeb(dataa=datab,)CLK,LPM_PIPELINEPWMT,T(tffout)Ttffclk2.4PWMPWM,55PWMDEADZONE(tffout),countq_temp,countq_temp,8,countq_temp256,12.8us(dzout)PWM(OUT1),PWM(OUT2)VHDL:entitydeadzoneisport(clk:instd_logic;wave:instd_logic;delaywave:outstd_logic);enddeadzone;architecturedeadofdeadzoneissignalcountq_temp:std_logic_vector(7downto0);beginprocess(wave,clk)beginifclkeventandclk=1thenifwave=1thenifcountq_temp11111111thencountq_temp=countq_temp+1;elsecountq_temp=11111111;delay2wave=1;endif;elsifwave=0thenifcountq_temp00000000thencountq_temp=countq_temp-1;elsecountq_temp=00000000;delay2wave=0;endif;elsenull;endif;endif;endprocess;enddead;3PWMPWMPWM,,,66PWMTffoutT,;TffclkT;Overflow(T);out1PWM;out2PWM;dzout;en1en212;clk1clk24CPLDPWM,,AtmelAT89S51AlteraEPM7128SLC842152PWM,(99)592,:VHDLCPLDPWM2(0.2s)22175.7673-76.48061234.4395-55.96742169.5152,b,,,176.9103A,-77.4617,0.65%,1,32.52%,,,,24.18%,4,3;Matlab,,;Mann2Morrison(Reference):[1].[M].:,1992.[2],,.[J].,2003,27(15):40-44.[3],.[J].,2005,17(4):41-43.[4],,.[J].,2007,35(6):16-20.[5],,.[J].,2005,33(17):11-13.[6],.[J].,2003,29(6):43-45.[7],,.[J].,1996,20(1):52-55.[8].[M].:,1986.[9],.Matlab[J].,2002,30(4):22-25.[:](95)(Reference):[1],.[M].:,1993.[2],.[M].:,2000.[3]ALTERA.MAX7000ProgrammableLogicDeviceFamilyDataSheet[EB/OL].[2001-11-01].[4]WUAM,XIAOJW,MARKOVICDJ,etal.DigitalPWMControl:ApplicationinVoltageRegulationModules[C].IEEEPESC99,1999(1):77-83.[5]PATELLABJ,PRODICA,ZIRGERA,etal.High2fre2quencydigitalPWMcontrollerICforDC/DCconverters[J].IEEETransactionsonPowerElectronics,2003,18(1):438-446.[6]BARONTIF,ADELLPC,HOLMANWT,etal.DC/DCSwitchingPowerConverterwithRadiationHardenedDigitalControlBasedonSRAMFPGA[C]//The7thAnnualMili2taryandAerospaceApplicationsofprogrammableDevicesandTechnologiesconference(MAPLD),WashingtonDC:NASAofficeoflogicDesign,2004:1-4.[7],.EDAVHDL[M].:,2005.[:]992,: