DDR2 协议规范 JESD79-2F

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JEDECSOLIDSTATETECHNOLOGYASSOCIATIONJESD79-2FNovember2009JEDECSTANDARDDDR2SDRAMSPECIFICATION(RevisionofJESD79-2E)NOTICEJEDECstandardsandpublicationscontainmaterialthathasbeenprepared,reviewed,andapprovedthroughtheJEDECBoardofDirectorslevelandsubsequentlyreviewedandapprovedbytheJEDEClegalCounsel.JEDECstandardsandpublicationsaredesignedtoservethepublicinterestthrougheliminatingmisunderstandingsbetweenmanufacturersandpurchasers,facilitatinginterchangeabilityandimprovementofproducts,andassistingthepurchaserinselectingandobtainingwithminimumdelaytheproperproductforusebythoseotherthanJEDECmembers,whetherthestandardistobeusedeitherdomesticallyorinternationally.JEDECstandardsandpublicationsareadoptedwithoutregardtowhetherornottheiradoptionmayinvolvepatentsorarticles,materials,orprocesses.BysuchactionJEDECdoesnotassumeanyliabilitytoanypatentowner,nordoesitassumeanyobligationwhatevertopartiesadoptingtheJEDECstandardsorpublications.TheinformationincludedinJEDECstandardsandpublicationsrepresentsasoundapproachtoproductspecificationandapplication,principallyfromthesolidstatedevicemanufacturerviewpoint.WithintheJEDECorganization,thereareprocedureswherebyaJEDECstandardorpublicationmyabefurtherprocessedandultimatelybecomeanANSIstandard.Noclaimstobeinconformancewiththisstandardmaybemadeunlessallrequirementsstatedinthestandardaremet.Inquiries,comments,andsuggestionsrelativetothecontentofthisJEDECstandardorpublicationshouldbeaddressedtoJEDECattheaddressbelow,orcall(703)907-7559or©JEDECSolidStateTechnologyAssociation20093103North10thStreet,Suite240-SArlington,VA22201Thisdocumentmaybedownloadedfreeofcharge,howeverJEDECretainsthecopyrightonthismaterial.Bydownloadingthisfiletheindividualagreesnottochargefororreselltheresultingmaterial.Price:PleaserefertothecurrentCatalogofJEDECEngineeringStandardsandPublicationsonlineat!DON’TVIOLATETHELAW!ThisdocumentiscopyrightedbytheElectronicIndustriesAllianceandmaynotbereproducedwithoutpermission.Organizationsmayobtainpermissiontoreproducealimitednumberofcopiesthroughenteringintoalicenseagreement.Forinformation,contact:JEDECSolidStateTechnologyAssociation2500WilsonBoulevardArlington,Virginia22201-3834orcall(703)907-7559Thispageintentionallyleftblank.JEDECStandardNo.79-2FContents1Scope.................................................................................................................................................12Packageballout&addressing.........................................................................................................22.1DDR2SDRAMpackageballout......................................................................................................22.2Quad-stacked/quad-dieDDR2SDRAMinternalrankassociations..............................................112.3Input/outputfunctionaldescription................................................................................................132.4DDR2SDRAMaddressing............................................................................................................143Functionaldescription...................................................................................................................163.1Simplifiedstatediagram................................................................................................................163.2Basicfunctionality.........................................................................................................................163.3Power-upandinitialization............................................................................................................163.3.1Power-upandinitializationsequence........................................................................................173.4Programmingthemodeandextendedmoderegisters.................................................................183.4.1DDR2SDRAMmoderegister(MR)...........................................................................................183.4.2DDR2SDRAMextendedmoderegisters(EMR(#))...................................................................193.4.3Off-chipdriver(OCD)impedanceadjustment............................................................................243.4.4ODT(on-dietermination)...........................................................................................................273.4.5ODTrelatedtimings...................................................................................................................273.5Bankactivatecommand................................................................................................................323.6Readandwriteaccessmodes......................................................................................................323.6.1PostedCAS...............................................................................................................................323.6.2Burstmodeoperation................

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