DDR2手册

JEDECSTANDARDDoubleDataRate(DDR)SDRAMJESD79F(RevisionofJESD79E,May2005)FEBRUARY2008JEDECSOLIDSTATETECHNOLOGYASSOCIATIONNOTICEJEDECstandardsandpublicationscontainmaterialthathasbeenprepared,reviewed,andapprovedthroughtheJEDECBoardofDirectorslevelandsubsequentlyreviewedandapprovedbytheJEDEClegalcounsel.JEDECstandardsandpublicationsaredesignedtoservethepublicinterestthrougheliminatingmisunderstandingsbetweenmanufacturersandpurchasers,facilitatinginterchangeabilityandimprovementofproducts,andassistingthepurchaserinselectingandobtainingwithminimumdelaytheproperproductforusebythoseotherthanJEDECmembers,whetherthestandardistobeusedeitherdomesticallyorinternationally.JEDECstandardsandpublicationsareadoptedwithoutregardtowhetherornottheiradoptionmayinvolvepatentsorarticles,materials,orprocesses.BysuchactionJEDECdoesnotassumeanyliabilitytoanypatentowner,nordoesitassumeanyobligationwhatevertopartiesadoptingtheJEDECstandardsorpublications.TheinformationincludedinJEDECstandardsandpublicationsrepresentsasoundapproachtoproductspecificationandapplication,principallyfromthesolidstatedevicemanufacturerviewpoint.WithintheJEDECorganizationthereareprocedureswherebyaJEDECstandardorpublicationmaybefurtherprocessedandultimatelybecomeanANSIstandard.Noclaimstobeinconformancewiththisstandardmaybemadeunlessallrequirementsstatedinthestandardaremet.Inquiries,comments,andsuggestionsrelativetothecontentofthisJEDECstandardorpublicationshouldbeaddressedtoJEDECattheaddressbelow,orreferto©JEDECSolidStateTechnologyAssociation20083103North10thStreetSuite240SouthArlington,VA22201-2107Thisdocumentmaybedownloadedfreeofcharge;howeverJEDECretainsthecopyrightonthismaterial.Bydownloadingthisfiletheindividualagreesnottochargefororreselltheresultingmaterial.PRICE:ContactJEDECPrintedintheU.S.A.AllrightsreservedPLEASE!DON’TVIOLATETHELAW!ThisdocumentiscopyrightedbyJEDECandmaynotbereproducedwithoutpermission.Organizationsmayobtainpermissiontoreproducealimitednumberofcopiesthroughenteringintoalicenseagreement.Forinformation,contact:JEDECSolidStateTechnologyAssociation3103North10thStreetSuite240SouthArlington,VA22201-2107orreferto(DDR)SDRAMSPECIFICATION16MX4(4MX4X4banks),8MX8(2MX8X4banks),4MX16(1MX16X4banks)32MX4(8MX4X4banks),16MX8(4MX8X4banks),8MX16(2MX16X4banks)64MX4(16MX4X4banks),32MX8(8MX8X4banks),16MX16(4MX16X4banks)128MX4(32MX4X4banks),64MX8(16MX8X4banks),32MX16(8MX16X4banks)256MX4(64MX4X4banks),128MX8(32MX8X4banks),64MX16(16MX16X4banks)FEATURES•Double--data--ratearchitecture;twodatatransfersperclockcycle•Bidirectional,datastrobe(DQS)istransmitted/re-ceivedwithdata,tobeusedincapturingdataatthereceiver•DQSisedge--alignedwithdataforREADs;cen-ter--alignedwithdataforWRITEs•Differentialclockinputs(CKandCK)•DLLalignsDQandDQStransitionswithCKtransi-tions•CommandsenteredoneachpositiveCKedge;dataanddatamaskreferencedtobothedgesofDQS•Fourinternalbanksforconcurrentoperation•Datamask(DM)forwritedata•Burstlengths:2,4,or8•CASLatency:2or2.5,DDR400alsoincludesCL=3•AUTOPRECHARGEoptionforeachburstaccess•AutoRefreshandSelfRefreshModes•2.5V(SSTL_2compatible)I/O•VDDQ:+2.5V±0.2VforDDR200,266,or333+2.6±0.1VforDDR400•VDD:+3.3V±0.3Vor+2.5V±0.2VforDDR200,266,or333+2.6±0.1VforDDR400GENERALDESCRIPTIONTheDDRSDRAMisahigh--speedCMOS,dynamicrandom--accessmemoryinternallyconfiguredasaquad--bankDRAM.Thesedevicescontainthefollow-ingnumberofbits:64Mbhas67,108,864bits128Mbhas134,217,728bits256Mbhas268,435,456bits512Mbhas536,870,912bits1Gbhas1,073,741,824bitsTheDDRSDRAMusesadouble--data--ratearchitec-turetoachievehigh--speedoperation.Thedoubledataratearchitectureisessentiallya2nprefetcharchi-tecturewithaninterfacedesignedtotransfertwodatawordsperclockcycleattheI/Opins.AsinglereadorwriteaccessfortheDDRSDRAMeffectivelyconsistsofasingle2n--bitwide,oneclockcycledatatransferattheinternalDRAMcoreandtwocorrespondingn--bitwide,one--half--clock--cycledatatransfersattheI/Opins.Abidirectionaldatastrobe(DQS)istransmittedex-ternally,alongwithdata,foruseindatacaptureatthereceiver.DQSisastrobetransmittedbytheDDRSDRAMduringREADsandbythememorycontrollerduringWRITEs.DQSisedge--alignedwithdataforREADsandcenter--alignedwithdataforWRITEs.TheDDRSDRAMoperatesfromadifferentialclock(CKandCK;thecrossingofCKgoingHIGHandCKgoingLOWwillbereferredtoasthepositiveedgeofCK).Commands(addressandcontrolsignals)arereg-isteredateverypositiveedgeofCK.Inputdataisregis-teredonbothedgesofDQS,andoutputdataisrefer-encedtobothedgesofDQS,aswellastobothedgesofCK.ReadandwriteaccessestotheDDRSDRAMareburstoriented;accessesstartataselectedlocationandcontinueforaprogrammednumberoflocationsinaprogrammedsequence.AccessesbeginwiththeregistrationofanACTIVEcommand,whichisthenfol-lowedbyaREADorWRITEcommand.TheaddressbitsregisteredcoincidentwiththeACTIVEcommandareusedtoselectthebankandrowtobeaccessed.TheaddressbitsregisteredcoincidentwiththeREADorWRITEcommandareusedtosele