EDA程序设计试题及答案

1．请画出下段程序的真值表，并说明该电路的功能。LIBRARYieee;USEieee.std_logic_1164.all;ENTITYaaaISPORT(oe,dir:INSTD_LOGIC;a,b:INOUTSTD_LOGIC_VECTOR(7DOWNTO0);ENDaaa;ARCHITECTUREarOFaaaISBEGINPROCESS(oe,dir)输入输出BEGINa1a0x3x2x1x0IFoe=’0’THENa=”zzzzzzzz”;b=”zzzzzzzz”;000001ELSIFoe=’1’THEN010010IFdir=’0’THENb=a;100100ELSIFdir=’1’THENa=b;111000ENDIF;ENDIF;ENDPROCESS;ENDar;功能为：2－4译码器…………………………………………..4分2．请说明下段程序的功能，写出真值表，并画出输入输出波形。LIBRARYieee;USEieee.std_logic_1164.all;USEieee.std_logic_arith.all;USEieee.std_logic_unsigned.all;ENTITYaaaISPORT(reset,clk:INSTD_LOGIC;q:BUFFERSTD_LOGIC_VECTOR(2DOWNTO0));ENDaaa;ARCHITECTUREbdOFaaaISBEGINPROCESS(clk,reset)BEGINIF(reset='0')THENq=000;ELSIF(clk'eventANDclk='1')THENIF(q=5)THENq=000;ELSEq=q+1;ENDIF;ENDIF;ENDPROCESS;ENDbd;功能为：带进位借位的4位加/减法器。…………………………………..3分输入输出波形图如下：………………………………………………………7分ma[3..0]b[3..0]c[3..0]d1.试用VHDL语言编程实现74LS273芯片的功能。LIBRARYieee;USEieee.std_logic_1164.ALL;2’ENTITYls273IS1’PORT(clr,clk:INstd_logic;d:INstd_logic_vector(7DOWNTO0);q:OUTstd_logic_vector(7DOWNTO0);4’);ENDls273;ARCHITECTURElock8OFls273IS1’BEGINPROCESS(clk)1’BEGINIF(CLR=’0’)THENq=”00000000”;2’ELSEIF(clk’eventANDclk=’1’)THENq=d;3’ELSEIF(clk=’0’)THENq=q;1’ENDIF;ENDPROCESS;ENDlock8;3.请用VHDL语言编程实现一个状态向量发生器。LIBRARYieee;USEieee.std_logic_1164.ALL;2’ENTITYstasIS1’PORT(cp,rst:INstd_logic;p:BUFFERstd_logic_vector(7DOWNTO0);2’);ENDstas;ARCHITECTUREarstasOFstasIS1’BEGINPROCESS(cp)1’BEGINIF(rst=”0”)THENp=”00000000”;1’ELSEIF(cp’eventANDcp=’1’)1’WITHpSELECTp=”10101010”WHEN“00000000”;”01010101”WHEN“10101010”;”00001111”WHEN“01010101”;”11110000”WHEN“00001111”;”11111111”WHEN“11110000”;”00000000”WHEN“11111111”;”00000000”WHENOTHERS;6’ENDIFENDPROCESS;ENDarstas;1.阅读下段程序，画出该电路的真值表，并详细说明该电路的功能。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYab_8ISPORT(a,b:INSTD_LOGIC_VECTOR(7DOWNTO0);ahb,alb,aeb:OUTSTD_LOGIC);ENDab_8;ARCHITECTUREbdOFab_8ISBEGINPROCESS(a,b)BEGINIFabTHENahb=’1’;alb=’0’;aeb=’0’;ELSIFabTHENahb=’0’;alb=’1’;aeb=’0’;ELSEahb=’0’;alb=’0’;aeb=’1’;ENDIF;ENDPROCESS;ENDbd;1.（1）真值表如下：(5’)输入输出a、bahbalbaebab100ab010a=b001（2）该电路是一个8位两输入比较器，（2’）a、b是两个8位输入端；（1’）ahb、alb和aeb为比较结果输出端，某种比较结果为真时，相应的输出端为“1”，其余端输出为“0”。（2’）1.试用VHDL语言编程实现一个2-4译码器，其真表如下：输入端输出端enselecty0XX“1111”100“1110”101“1101”110“1011”111“0111”2-4译码器码参考程序如下：（答案不唯一，用case语句、with…select语句都可以。）LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;(1’)ENTITYym24ISPORT(en:INSTD_LOGIC;select:OUTSTD_LOGIC_VECTOR(1DOWNTO0);y:OUTSTD_LOGIC_VECTOR(3DOWNTO0)(3’));ENDym24;ARCHITECTUREbdOFym24ISBEGINPROCESS(en)(1’)IF(en=’1’)THENy=”1110”WHENselect=”00”ELSE”1101”WHENselect=”01”ELSE”1011”WHENselect=”10”ELSE”0111”WHENselect=”11”ELSE(4’)”1111”;ELSEy=”1111”;ENDPROCESS;ENDbd;2.试用VHDL语言设计一个六路8位总线复用器，其中A、B、C、D、E、F都是8位输入总线，Q为8位输出总线，S为3位选择端，其功能如下：输入端输出端S2S1S0Q7~Q0000Q=A001Q=B010Q=C011Q=D100Q=E101Q=F其它B=“00000000”六路8位总线复用器参考程序：（答案不唯一）LIBRARYieee;USEieee.std_logic_1164.ALL;ENTITYmux6IS(1’)PORT(S:INstd_logic_vector(2DOWNTO0);A,B,C,D,E,F:INstd_logic_vector(7DOWNTO0);Q:OUTstd_logic_vector(7DOWNTO0));(3’)ENDmux6;ARCHITECTUREbdOFmux6ISBEGINPROCESS(S)BEGIN(1’)CASESISWHEN000=Q=A;WHEN001=Q=B;WHEN010=Q=C;WHEN011=Q=D;WHEN100=Q=E;WHEN101=Q=F;WHENOTHERS=Q=00000000;(4’)ENDCASE;ENDPROCESS;ENDbd;2、已知三选一电路如图，判断下列程序是否有错误，如有则指出错误所在，并给出完整程序。（10分）libraryieee;useieee.std_logic_1164.all;ENTITYMAXisport(a1,a2,a3,s0,s1:inbit;outy:outbit);endmax;（2’）architectureoneofmaxiscomponentmux21aport(a,b,s:instd_logic;y:outstd_logic);endcomponent;（2’）signaltempstd_logic;（2’）beginu1:mux21aportmap(a2,a3,s0,temp);（2’）u2:mux21aportmap(a1,temp,s1,outy);（2’）endone;1.已知电路原理图如下，请用VHDL语言编写其程序答：libraryieee;useieee.std_logic_1164.all;entitymux21isport(a,b,s:inbit;y:outbit);endmux21;（4’）architectureoneofmux21issingled,e:bit;begind=aand(not)s;e=bands;y=dore;endone;2.设计一个带有异步清零功能的十进制计数器。计数器时钟clk上升沿有效、清零端CLRN、进位输出co。答：libraryieee;useieee.std_logic_1164.all;entitycounter10isport(clk,CLRN:instd_logic;dout:outintegerrange0to9);endcounter10;（5’）architecturebehavofcounter10ISbeginprocess(clk)variablecnt:integerrange0to9;（3’）beginIFCLRN='0'THENCNT:=0;ELSIFclk='1'andclk'eventthenifcnt=9thencnt:=0;elsecnt:=cnt+1;endif;endif;dout=cnt;endprocess;endbehav;（7’）3．1）用VHDL语言编写半加器和或门器件的程序，如图所示：答：半加器程序：libraryieee;useieee.std_logic_1164.all;entityh_adderisport(a,b:instd_logic;co,so:outstd_logic);endh_adder;（2’）architectureoneofh_adderisbeginso=not(axor(notb));co=aandb;endone;（3’）或门程序：libraryieee;useieee.std_logic_1164.all;entityor2aisport(a,b:instd_logic;c:outstd_logic);endor2a;（2’）architectureoneofor2aisbeginc=aorb;endone;2）在上道题目的基础上用元件例化语句设计1位全加器。主程序：libraryieee;useieee.std_logic_1164.all;entityf_adderisport(ain,bin,cin:instd_logic;cout,sum:outstd_logic);endentityf_adder;architecturefd1off_adderiscomponenth_adderport(a,b:instd_logic;co,so:outstd_logic);endcomponent;（5’）componentor2aport(a,b:instd_logic;c:outstd_logic);endcomponent;signald,e,f:std_logic;beginu1:h_adderportmap(a=ain,b=bin,co=d,so=e);u2:h_adderportmap(a=e,b=cin,co=f,so=sum);u3:or2aportmap(d,f,cout);endfd1;（5’）1.试用VHDL语言编程实现一个总线开关，其真值表如下：输入输出ens