FE2.1 Data Sheet

USB2.07-PortHubDataSheetRev.0.9FE2.1USB2.0HIGHSPEED7-PORTHUBCONTROLLER_______________________DataSheet_______________________INTRODUCTIONTheFE2.1isahighlyintegrated,highquality,highperformance,lowpowerconsumption,yetlowoverallcostsolutionforUSB2.0HighSpeed7-PortHub.ItadoptsMultipleTransactionTranslator(MTT)architecturetoexplorethemaximumpossiblethroughput.Six,insteadoftwo,non-periodictransactionbuffersareusedtominimizepotentialtrafficjamming.Thewholedesignisbasedonstate-machine-controltoreducetheresponsedelaytime;nomicrocontrollerisusedinthischip.Toguaranteehighquality,thewholechipiscoveredbyTestScanChain–includeeventhehighspeed(480MHz)modules,sothatallthelogiccomponentscouldbefullytestedbeforeshipping.SpecialBuild-In-Self-Testmodeisdesignedtoexerciseallhigh,full,andlowspeedAnalogFrontEnd(AFE)componentsinthepackagingandtestingstagesaswell.Lowpowerconsumptionisachievedbyusing0.18μmtechnologyandcomprehensivepower/clockcontrolmechanism.Mostpartofthechipwillnotbeclockedunlessneeded.FEATURESLowpowerconsumption□155mAwhensevendownstreamfacingportsenabledinHigh-Speedmode;□66mAwhenonedownstreamfacingportenabledinHigh-Speedmode;FullycompliantwithUniversalSerialBusSpecificationRevision2.0(USB2.0);□UpstreamfacingportsupportsHigh-Speed(480MHz)andFull-Speed(12MHz)modes;□7downstreamfacingportssupportHigh-Speed(480MHz),Full-Speed(12MHz),andLow-Speed(1.5MHz)modes;IntegratedUSB2.0Transceivers;Integratedupstream1.5KΩpull-up,downstream15KΩpull-down,andserialresisters;Integrated5Vto3.3Vand1.8Vregulator.IntegratedPower-On-Resetcircuit;Integrated12MHzOscillatorwithfeedbackresisterandcrystalloadcapacitor;Integrated12MHz-to-480MHzPhaseLockLoop(PLL);MultipleTransactionTranslator(MTT)–□OneTTforeachdownstreamport;
 

 
第1页共23页□AlternateInterface0forSingle-TT,andAlternateInterface1forMultiple-TT;□EachTTcouldhandle64periodicStart-Splittransactions,32periodicComplete-Splittransactions,and6none-periodictransactions;SupportSelf-PoweredModeonly;Boardconfiguredoptions–□GangedorIndividualPowerControlModeselect;□Global,MultipleGanges,orIndividualOver-CurrentProtectionModeselect;□RemovableorNon-RemovableDownstreamDevicesconfiguration;□NumberofDownstreamPorts;EEPROMconfiguredoptions–□VendorID,ProductID,&DeviceReleaseNumber;□RemovableorNon-RemovableDownstreamDevicesconfiguration;□SerialNumber;and□NumberofDownstreamPorts;Comprehensivestatusindicatorssupport:□Standarddownstreamportstatusindicators(GreenandAmberLEDcontrolforeachdownstreamport);□HubActive/SuspendindicatorLED.
 

 
第2页共23页BLOCKDIAGRAMFig.1:BlockDiagramDown-streamPHY#1Down-streamPHY#2∙∙∙∙∙Down-streamPHY#7UpstreamPHYRoutingSwitchDataTransmitDataRecovery&ElasticityBufferPLL(x40)3.3V&1.8VRegulatorPORUSBMulti-portTransceiverMacroCellSIEDownstreamPortControllersUpstreamPortControllerTransactionTranslatorFull/Low-SpeedHandlerTransactionTranslatorHigh-SpeedHandlerHubControllerLEDControllerUnifiedTransactionTranslatorBuffer(14KB)USB2.0HubControllerOSC12MHzCrystalToDownstreamDevicesToUpstreamHost/HubPortIndicatorsEEPROM,HubActivityLEDOverCurrentDetectionPowerSwitchControl
 

 
第3页共23页PACKAGEI–64-PINLQFP(BodySize:10x10mm)PINASSIGNMENTFig.2:64-pinLQFPPinAssignmentDRVFE2.1117163233484964DM4VD18_OVSSTESTJLED[5]LED[1]LED[2]LED[3]VD18LED[4]VDD5VD33_OVSSPWRJ[3]OVCJ[3]PWRJ[4]OVCJ[4]VD33DP4VSSDM3DP3VD33DM2DP2VSSDM1DP1VD33VD_PLLXINXOUTVS_PLLVD33REXTVD18VSSDMUDPUVD33DM5DP5VSSDM6DP6VD33DM7DP7XRSTJVBUSMLED[6]LED[7]PWRJ[7]OVCJ[7]VD33PWRJ[6]OVCJ[6]PWRJ[5]OVCJ[5]PWRJ[1]OVCJ[1]PWRJ[2]OVCJ[2]
 

 
第4页共23页PACKAGEII–48-PINLQFP(BodySize:7x7mm)PINASSIGNMENTFig.3:48-pinLQFPPinAssignmentFE2.1113122425363748VD18_OVSSTESTJLED[1]LED[2]LED[3]VD18LED[4]VDD5VD33_OVSSDRVDM3DP3VD33DM2DP2DM1DP1VD33VD_PLLXINXOUTVS_PLLVD33REXTVD18DMUDPUVD33DM5DP5DM6DP6VD33XRSTJVBUSMLED[5]VD33PWRJOVCJ1LED[7]LED[6]DP7DM7DM4DP4OVCJ5
 

 
第5页共23页PINDESCRIPTIONTABLEPinName64-pinLQFPPin#48-pinLQFPPin#TypeFunctionNoteLED[5]148OLEDControlforthe5thDownstreamFacingPortStatus.DRV21ODrivingControlforallLED.TESTJ32IO-PUTestModeEnableduringhardwarereset,activelow.Otherwise,SDA,SerialData/AddresspinforexternalSerialEEPROM.LED[1]43O/IO-PULEDControlforthe1stDownstreamFacingPortStatus,andSCL,SerialClockpinforexternalSerialEEPROM.4LED[2]54O/I-PULEDControlforthe2ndDownstreamFacingPortStatus,andNon-RemovableDeviceConfigurationbit0.3LED[3]65O/I-PULEDControlforthe3rdDownstreamFacingPortStatus,andNon-RemovableDeviceConfigurationbit1.3VD187,366,28P1.8Vpowerinput.LED[4]87O/I-PULEDControlforthe4thDownstreamFacingPortStatus,andNon-RemovableDeviceConfigurationbit2.3VDD598P5Vpowerinputforintegrated5V→3.3Vregulator.VD33_O109P3.3Vpoweroutputfrom5V→3.3Vintegratedregulator–a10μFdecouplingcapacitorisrequired.VSS11,19,25,37,43,4910,39PGround.PWRJ[3]12―ODPowerEnablefor3rdDownstreamFacingPort,activelow.OVCJ[3]13―I-PUOver-currentDetectfor3rdDownstreamFacingPort,activelow.1PWRJ[4]14―ODPowerEnablefor4thDownstre