Cadence Allegro SI培训课件Lesson2

LearningObjectives1Lesson2AllegroPCBSIDesignFlow:Pre-PlacementIdentifyboarddatabasesetuprequirements.UsetheDatabaseSetupAdvisortosetupaboarddatabase.UsetheSignalAnalysisLibraryBrowser.TranslateIBIS(.ibs)signalmodelsintoCadenceDeviceModelLibrary(.dml)format.2TheAllegroPCBSIDesignFlowPre-PlacementSolutionSpaceAnalysisConstraint-DrivenFloorplanningConstraint-DrivenRoutingPost-RouteDRCPost-RouteAnalysisTheAllegroPCBSIDesignFlowconsistsofthefollowingsixsteps:EYouareHereDoubleClickHeretoOpentheImage3DesignFlow:Pre-PlacementStandardformfactors,mechanicalrestrictions,andstandardpracticesoftenpredefinelocationsofcriticalcomponents.Electricaldesignmuststartwiththeserequirements,orpresentastrongcasewhythingsshouldbechanged.Pre-placeddesignisusuallycreatedbytheCADgroupasastartingpointfordesign.Chipsetplacementpredetermined4BoardSetupRequirementsAllegroPCBSIneedsseveralitemsinplacetocorrectlyextractandapplytopologytemplates.Theseitemsare:AnetlistAboardfilewithadefinedlayoutcross-sectionIdentificationofDCnets&assignmentoftheirDCVALUEpropertyProperlyassignedCLASSpropertiesonthecomponentsSimulationmodelsforthecomponentsassociatedwiththetopologyProperlyassignedpropertiesonthepinsofcomponents5DatabaseSetupAdvisorThefirstscreenoftheDatabaseSeupAdvisor.ExplainstheuseofDatabaseSetupAdvisor.Describesthestepsyoumusttaketosetupthedatabasecorrectly.“SetupRight,SetupOnce”.Click‘Next’toproceedtothenextstepintheprocesstocompletetheDatabaseSetup.6DatabaseSetupAdvisor:Cross-sectionExplainstheuseoflayoutcross-sectioninthesimulation.Describesthestepstoeditlayoutcross-section.ClickheretoopentheLayoutCross-sectionEditor7WhatistheLayoutCross-Section?Thelayoutcrosssectiondefinesthephysicalandelectricalcharacteristicsoftheprintedcircuitboard.Boardcrosssectiondefinesconductoranddielectric(insulator)layers.Determinesoverallboardthickness.Tracewidthandboardcross-sectiondeterminetracecharacteristics.Distancebetweentracesandreferenceplaneshasprimaryeffecton:Impedance:increaseswithdistanceCrosstalk:increaseswithdistance8DefiningtheLayoutCross-SectionFromtheAllegroPCBSImenuselectSetupCross-Section.LayoutCross-Sectioneditorconsistsoforderedlayersofyourboard.Designatesthecurrentlyselectedlayerasaelectricalsignalsfromthetwoadjacentshieldlayer.Theshieldlayerpreventsthelayersfrominteractingwitheachother.ActivateDifferentialModeLayoutCrossSectionEditor9MaterialsEditorTypethecommand“definematerials”attheCommandpromptofthetoolcommandconsoletoinvokeMaterialsEditor.FromAllegroPCBSImenuselectSetupMaterials.10DCVoltagesAllegroPCBSIneedssourcevoltagesforterminatorsandcapacitorstobuildanelectricallycorrectcircuit.Terminatedbusesto1.5Volts11DatabaseSetupadvisor:DCNetsFromtheAllegroPCBSImenuselect:ToolsSetupAdvisor.DescribesthestepstoidentifytheDCNets.ClicktoselecttheNetfromthelistVoltagelevelcurrentlyassignedtotheselectedNetYoucanalsoinvoketheIdentifyDCNetsformfromtheAllegroPCBSImenubyselecting:LogicIdentifyDCNets.Uses12DeviceCLASSandPINUSEPropertiesICs(Active)Resistors,Inductors,Capacitors(Passive)ConnectorsICDISCRETEIOINPUT,OUTPUT,BI,TRISTATE,POWER,GROUND,OCA,OCL,NCUNSPECUNSPECIBIS(mayincludeMacromodels)-dmlESpice-dmlSpicesubcktsandRLGCmatrixformatswithdmlwrappers-dmlComponentTypeCLASSPINUSESignalModelTypePCBSIneedsthismodeltotraceXnetconnectivity.Extractionandanalysiswillfailotherwise.PCBSIusesthistodeterminebuffertypeforSigXplorerandSigNoisesimulations.PINUSEmustmatchbetweentopologytemplateanddesignwhentemplatesareapplied(dependingonthemappingstrategyused).MaybeusedtomodelparasiticsbetweenboardsNotes13DatabaseSetupAdvisor:DeviceSetupFromtheAllegroPCBSImenuselect:ToolsSetupAdvisor.14EditingthePartsListFromtheAllegroPCBSImenuselect:LogicPartsList.CurrentPartsListICIODISCRETEChoosethepartsfromtheselibraries.Classassignmentforthecomponents.Assign/Modifycomponentinformation15EditingPinTypesFromtheAllegroPCBSImenuselect:LogicPinType.ComponentsorNetListingsSelectedComponentPinsAvailablePinTypes16Lab:BoardSetupRequirements–Session1RuntheDatabaseSetupAdvisorEditLayoutCross-sectionIdentifyDCNetsCorrectCLASSandPINUSEpropertiesassignedtothecomponentsLabTheBoardSetupRequirementlabwillbecontinuedinthenextlabsession.17DatabaseSetupadvisor–SIModelsRLCRLCRLCIBISDeviceModelIBISIOCellModelPackageModelSignalModel18SignalModelAssignmentFormFromtheAllegroPCBSImenuselect:AnalyzeSI/EMISimModel.AssignedModelsModellibrarylocationInvokesappropriateeditortomodifytheselectedmodelDisplaystheSigNoisePreferenceDisplaystheModelBrowserDisplaysthecorrectCreateModelformforthemodelselectedListoftheboardcomponents19AutosetupofModelsFromtheAllegroPCBSImenuselect:AnalyzeSI/EMISimModel.TheSignalModelslocatedinthelibraryareassociatedtothedevicesNewmodelscreatedarestoredinWorkingDeviceLibraryAutoSetupComponents20SignalAnalysisLibraryBrowserFromtheSigXplorer-PCBSImenuselect:AnalyzeLibrariesorfromAllegroPCBSImenuselect:AnalyzeSI/EMISimLibrary.CurrentworkinglibrariesDeviceLibrariessectionInterconnectlibrariessection=21TranslatingandAddingLibrariesAnIndexfile