CY7C4235-15JI中文资料

64,256,512,1K,2K,4Kx18SynchronousFIFOsfaxid:5410CY7C4425/4205/4215CY7C4225/4235/4245CypressSemiconductorCorporation•3901NorthFirstStreet•SanJose•CA95134•408-943-2600April1995-RevisedAugust18,19971CY7C4225Features•High-speed,low-power,first-infirst-out(FIFO)memories•64x18(CY7C4425)•256x18(CY7C4205)•512x18(CY7C4215)•1Kx18(CY7C4225)•2Kx18(CY7C4235)•4Kx18(CY7C4245)•High-speed100-MHzoperation(10nsread/writecycletime)•Lowpower(ICC=45mA)•Fullyasynchronousandsimultaneousreadandwriteoperation•Empty,Full,HalfFull,andProgrammableAlmostEmpty/AlmostFullstatusflags•TTL-compatible•Retransmitfunction•OutputEnable(OE)pin•Independentreadandwriteenablepins•Centerpowerandgroundforreducednoise•Supportsfree-running50%dutycycleclockinputs•WidthExpansionCapability•DepthExpansionCapability•Spacesaving64-pin10x10TQFP,and14x14TQFP•68-pinPLCCFunctionalDescriptionTheCY7C42X5arehigh-speed,low-power,first-infirst-out(FIFO)memorieswithclockedreadandwriteinterfaces.Allare18bitswideandarepin/functionallycompatibletoIDT722x5.TheCY7C42X5canbecascadedtoincreaseFIFOdepth.ProgrammablefeaturesincludeAlmostFull/AlmostEmptyflags.TheseFIFOsprovidesolutionsforawidevarietyofdatabufferingneeds,includinghigh-speeddataacquisition,multiprocessorinterfaces,andcommunicationsbuffering.TheseFIFOshave18-bitinputandoutputportsthatarecon-trolledbyseparateclockandenablesignals.Theinputportiscontrolledbyafree-runningclock(WCLK)andawriteenablepin(WEN).WhenWENisasserted,dataiswrittenintotheFIFOontherisingedgeoftheWCLKsignal.WhileWENisheldactive,dataiscontinuallywrittenintotheFIFOoneachcycle.Theoutputportiscontrolledinasimilarmannerbyafree-runningreadclock(RCLK)andareadenablepin(REN).Inaddition,theCY7C42X5haveanoutputenablepin(OE).Thereadandwriteclocksmaybetiedtogetherforsingle-clockoperationorthetwoclocksmayberunindependentlyforasynchronousread/writeapplications.Clockfrequenciesupto100MHzareachievable.RetransmitandSynchronousAlmostFull/AlmostEmptyflagfeaturesareavailableonthesedevices.Depthexpansionispossibleusingthecascadeinput(WXI,RXI),cascadeoutput(WXO,RXO),andFirstLoad(FL)pins.TheWXOandRXOpinsareconnectedtotheWXIandRXIpinsofthenextdevice,andtheWXOandRXOpinsofthelastdeviceshouldbeconnectedtotheWXIandRXIpinsofthefirstdevice.TheFLpinofthefirstdeviceistiedtoVSSandtheFLpinofalltheremainingdevicesshouldbetiedtoVCC.TheCY7C42X5providesfivestatuspins.Thesepinsarede-codedtodetermineoneoffivestates:Empty,AlmostEmpty,HalfFull,AlmostFull,andFull(seeTable2).TheHalfFullflagsharestheWXOpin.Thisflagisvalidinthestandaloneandwidth-expansionconfigurations.Inthedepthexpansion,thispinprovidestheexpansionout(WXO)informationthatisusedtosignalthenextFIFOwhenitwillbeactivated.TheEmptyandFullflagsaresynchronous,i.e.,theychangestaterelativetoeitherthereadclock(RCLK)orthewriteclock(WCLK).WhenenteringorexitingtheEmptystates,theflagisupdatedexclusivelybytheRCLK.TheflagdenotingFullstatesisupdatedexclusivelybyWCLK.Thesynchronousflagarchi-tectureguaranteesthattheflagswillremainvalidfromoneclockcycletothenext.Asmentionedpreviously,theAlmostEmpty/AlmostFullflagsbecomesynchronousiftheVCC/SMODEistiedtoVSS.Allconfigurationsarefabricatedusinganadvanced0.65μN-WellCMOStechnology.InputESDprotectionisgreaterthan2001V,andlatch-upisprevent-edbytheuseofguardrings.CY7C4425/4205/4215CY7C4225/4235/42452LogicBlockDiagram42X5–1THREE–STATEOUTPUTREGISTERREADCONTROLFLAGLOGICWRITECONTROLWRITEPOINTERREADPOINTERRESETLOGICEXPANSIONLOGICINPUTREGISTERFLAGPROGRAMREGISTERD0–17RENRCLKFFEFPAEQ0–17WENWCLKRSFL/RTWXIOEDUALPORTRAMARRAY64x18256x18512x181Kx182Kx184Kx18PAFWXO/HFRXIRXOSMODEPinConfigurationsEF10111213141516171819202122232467TopView60595857565554535251504948313233343536373839404142435432168666564636261Q14Q13GNDQ12Q11VCCQ10Q9GNDQ8Q7VCCD14D13D12D11D10D9VCCD8GNDD7D6D5D427282930987647464544Q6Q5GNDQ4D3D2D1D02526VCC/SMODE42x5–2TQFPTopView42X5–312345678910111213141548474645444342414039383736353433176418631962206121602259235824572556265527542853295230513150324916PLCCPAEFL/RTWCLKWENWXIVCCPAFRXIFFWXO/HFRXOQ0Q1GNDQ2Q3VCCQ15GNDQ16Q17VCCEFGNDVCCRSOELDRENRCLKGNDD17D16D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0D15Q15GNDQ16Q17GNDVCCRSOELDRENRCLKGNDD17D16PAEWCLKWENWXIVCCPAFRXIFFWXO/HFRXOQ0Q1GNDQ2Q3Q14Q13GNDQ12Q11VCCQ10Q9GNDQ8Q7Q6Q5GNDQ4VCCVCC/SMODEFL/RTCY7C4425CY7C4205CY7C4215CY7C4225CY7C4235CY7C4245CY7C4425CY7C4205CY7C4215CY7C4225CY7C4235CY7C4245CY7C4425/4205/4215CY7C4225/4235/42453SelectionGuide7C42X5-107C42X5-157C42X5-257C42X5-35MaximumFrequency(MHz)10066.74028.6MaximumAccessTime(ns)8101520MinimumCycleTime(ns)10152535MinimumDataorEnableSet-Up(ns)3467MinimumDataorEnableHold(ns)0.5112MaximumFlagDelay(ns)8101520OperatingCurrent(ICC2)(mA)@freq=20MHzCommercial45454545Industrial50505050CY7C4425CY7C4205CY7C4215CY7C4225CY7C4235CY7C4245Density64x18256x18512x181Kx182Kx184Kx18Packages68-pinPLCC64-pinTQFP(10x10/14x14)68-pinPLCC64-pinTQFP(10x10/14x14)68-pinPLCC64-pinTQFP(10x10/14x14)68-pinPLCC64-pinTQFP(10x10/14x14)68-pinPLCC64-pinTQFP(10x10/14x14)68-pinPLCC64-pinTQFP(10x10/14x14)PinDefinitionsSignalNameDescriptionI/OFunctionD0–17DataInputsIDatainput