Cyclone II EP2C70 DSP Development Board Schematic

8877665544332211EEDDCCBBAAPLLDACADCTitleSizeDocumentNumberRevDate:Sheetof150-0310202-C1(6XX-40023R)CCycloneIIDSPBoardB122Tuesday,August15,2006TitleSizeDocumentNumberRevDate:Sheetof150-0310202-C1(6XX-40023R)CCycloneIIDSPBoardB122Tuesday,August15,2006TitleSizeDocumentNumberRevDate:Sheetof150-0310202-C1(6XX-40023R)CCycloneIIDSPBoardB122Tuesday,August15,2006Copyright(c)2005,AlteraCorporation.AllRightsReserved.DESCRIPTIONREVDATEPAGESPAGEDESCRIPTION2NOTES:Title,Notes,BlockDiagram,RevisionHistory13478CycloneIIBanks5&69CycloneIIBanks7&8101112131415DigitalPowerSupplies16DDR2Termination17CycloneIIConfigurationCircuitry18ADCChannelA19DACChannelA20DACChannelB21VideoDAC22-----23ADCChannelB2425-----AlteraCorporation,9330ScrantonRd#400,SanDiego,CA92121SRAM,TIEVMConnectorsAnalogPowerSupplies56AIC23AudioCodecButtons,Switches,LEDsDigitalGround894Parts,63LibraryParts,874Nets,4299PinsFPGAPackageI/ODiagram&DesignNotesSystemBlockDiagram1.ProjectDrawingNumbers:RawPCBGerberFilesPCBDesignFilesAssemblyDrawingFabDrawingSchematicDrawingPCBFilmBillofMaterialsSchematicDesignFilesFunctionalSpecificationPCBLayoutGuidelinesAssemblyReworkClockCircuitryCycloneIIBanks3&4CycloneIIBanks1&2DDR2DIMM2.100-0310202-C1110-0310202-C1120-0310202-C1130-0310202-C1140-0310202-C1150-0310202-C1160-0310202-C1170-0310202-C1180-0310202-C1210-0310202-C1220-0310202-C1320-0310202-C1CycloneIIPowerandDecouplingAlteraDaughterCard&MictorConnectorPLLGround-----DACGroundADCGroundA01/26/2005-----ReleasedforProtoypeProductionB-----02/17/2005FixedclockbufferU27pinout.FixedSSRAMU22pinouttoremoverework.FixedEVM_CE2/CE3shortonTIEVMInterface.FixedVTTRegulatorU8decouplingbyaddingceramicoutputcaps.04/04/2006C1,16FixedgroundconnectionsonAIC23audiocodec(U11).8877665544332211EEDDCCBBAATitleSizeDocumentNumberRevDate:Sheetof150-0310202-C1CCycloneIIDSPBoardB222Sunday,August13,2006TitleSizeDocumentNumberRevDate:Sheetof150-0310202-C1CCycloneIIDSPBoardB222Sunday,August13,2006TitleSizeDocumentNumberRevDate:Sheetof150-0310202-C1CCycloneIIDSPBoardB222Sunday,August13,2006BANK8(a)AlteraCorporation,9330ScrantonRd#400,SanDiego,CA92121(l)1.BANK3BANK5(k)Bank5-I/ONotes:BANK2DACChannel2Bank3-I/OBank8-I/OBank4-I/O(b)Bank2-I/OBank7-I/OVCCIO=1.8VVCCIO=3.3VFPGASchematicSymbolBreakdown:2.VCCio,GNDBANK6(i)(f)PCBSupports2C70-2C50-2C70MigrationVCCIO=1.8VVCCIO=1.8VFPGAPackageTopViewBank6-I/O(h)VCCint,GNDBANK1BANK7(j)BANK4VCCIO=3.3VBank1-I/OClocksVCCIO=1.8VVCCIO=3.3V(d)(c)Copyright(c)2005,AlteraCorporation.AllRightsReserved.VCCIO=3.3V(e)(g)ConfigurationSharedBusDACChannel1SharedBusDACChannel2DDR2DIMMDATALANESADCChannel2DDR2DIMMDATALANESADCChannel2ProtoBusVideoDACDACChannel1DACChannel1DACChannel2VideoDACDDR2DIMMDATALANES,CNTL,CLOCKPushbuttonsDDR2DIMMDATALANES,ADDRESSPushbuttonsDipswitch(2C70DeviceShown)NoadditionalI/Oof2C70or2C50usedasADCChannel1VideoDACthe2C70hasthefewestI/OofthegroupduetoadditionalVCCINT,GND,andVREFpinsonthelarger2C50and2C70devices.3.SomeI/Opinsareconnectedto1.2VandGND.ThesearetheadditionalVCCandGNDpinsofthelarger2C50and2C70.DONOTDRIVEUNUSEDI/OTOGNDINQUARTUS---WARNING---Leaving1.2V-connectedI/OpinsasoutputsdrivingGNDcauseshighI/Ocurrentandincreasedtemperaturewhichcanleadtodevicedamageifleftoveralongperiodoftime.8877665544332211EEDDCCBBAA3.3V_OSCBCLK_SELCLK_SMACLK_OSCCLK_EN3.3V_CLKCLKIN_BOTCLKIN_TOPCLKIN_BOT_RCLKIN_TOP_R3.3V_CLKADCA_ENCADCB_ENCCLK_OSC_ADCBCLK_OSC_ADCACLK_OSC_DACB_RCLK_OSC_ADCB_RCLK_OSC_ADCA_RFPGA_TO_ADC_CLKFPGA_TO_ADC_CLKCLK_OSC_DACACLK_OSC_DACBFPGA_TO_DAC_CLKFPGA_TO_DAC_CLKSMA_TO_ADC_CLKSMA_TO_DAC_CLKSMA_TO_DAC_CLKSMA_TO_ADC_CLKCLK_OSC_DACA_RPROTO_CLK_OSC_RCLKIN_TOPCLKIN_BOTSMA_TO_ADC_CLKSMA_TO_DAC_CLKDACA_ENCDACB_ENCDACA_CLK_RDACB_CLK_R3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3V3.3VADC_A_CLK_P11ADC_A_CLK_N11ADC_B_CLK_P12ADC_B_CLK_N12DACA_CLK13DACB_CLK14FPGA_TO_ADC_CLK4FPGA_TO_DAC_CLK4USER_LED717DAC_B_D314PROTO_IO319USER_LED217DAC_B_D414USER_LED017USER_LED617PROTO_CLK_OSC19EVM_CLKOUT218VGA_VSYNC15EVM_INUM018EVM_RESET18EVM_AREn18EVM_IACK18USER_DIPSW017DIMM_SYNC_CLK7USER_PB317AUDIO_DOUT16ADC_A_DCLK11ADC_B_DCLK12ADC_A_D711PROTO_CLKOUT19TitleSizeDocumentNumberRevDate:Sheetof150-0310202-C1CCycloneIIDSPBoardB322Tuesday,August15,2006TitleSizeDocumentNumberRevDate:Sheetof150-0310202-C1CCycloneIIDSPBoardB322Tuesday,August15,2006TitleSizeDocumentNumberRevDate:Sheetof150-0310202-C1CCycloneIIDSPBoardB322Tuesday,August15,2006Copyright(c)2005,AlteraCorporation.AllRightsReserved.AlteraCorporation,9330ScrantonRd#400,SanDiego,CA92121CycloneIIClockingPIN2-PIN3SMAInputOscillatorDualfootprintwithSMTandsocketedoscillatorSocketCLK100MHzCLKPIN2-PIN3PIN1-PIN2SMAInputPIN1-PIN2High-SpeedClockSourceOn-BoardOSCCustomOSC(1)On-BoardOSC(2)CustomOSC(3)SMAInputChannelAADCClockSMAADCSampleClockADCSampleClockChannelBDACClockSMADACClock(fromFPGA)ADCClock(fromFPGA)ADCClockSelectChannelAADCClockSelectChannelBDACClockSelectChannelADACClockSelectChannelBDACSampleClockDACSampleClockChannelBChannelAR24582RR24582RR12549.9R12549.9R25982RR25982RC3980.01ufC3980.01ufJ26LTI-SASF54GTJ26LTI-SASF54GT12