计算结构POC报告

TheDesignReportoftheparalleloutputcontroller(POC)1ComputerOrganizationandArchitectureCourseDesignTheReportoftheparalleloutputcontroller(POC)SchoolofInformationScienceandEngineeringSoutheastUniversityMarch2012NameShixiYuStudentNumber04009528TheDesignReportoftheparalleloutputcontroller(POC)2PurposeThepurposeofthisprojectistodesignandsimulateaparalleloutputcontroller(POC)whichactsaninterfacebetweensystembusandprinter.TheAltera’sMaxplusIIEDAtoolisrecommendedandprovidedforsimulation.PleaserefertoWilliam,Stallings.“ComputerOrganizationandArchitecture,DesigningforPerformance”,P.65~75;P.185~190.TaskandPrincipleBasicintroductionPOCisoneofthemostcommonI/Omodules,namelytheparalleloutputcontroller.Itplaystheroleofaninterfacebetweenthecomputersystembusandtheperipheral(suchasaprinterorotheroutputdevices).ArchitecturalModelFigure1PrinterConnectionFigure1showstheconnectingofaprintertothesystembusthroughthePOC.ThecommunicationbetweenPOCandtheprinteriscontrolledbya“handshake”protocolTheDesignReportoftheparalleloutputcontroller(POC)3illustratedinFigure2.Figure2Thehandshake-timingdiagrambetweenPOCandtheprinterThehandshakingprocessisdescribedasfollows:Whentheprinterisreadytoreceiveacharacter,itholdsRDY=1.ThePOCmustthenholdacharacteratPD(paralleldata)portandproduceapulseattheterminalTR(transferrequest).TheprinterwillchangeRDYto0,takethecharacteratPDandholdtheRDYat0untilthecharacterhasbeenprinted(e.g.5or10ms),thensetRDY=1againwhenitisreadytoreceivethenextcharacter.(Supposetheprinterhasonlyaonecharacter“buffer”register,sothateachcharactermustbeprintedbeforethenextcharacterissent).PrincipleofthemodelInordertoeaseyourdesignwork,thefurtherexplanationsofthePOCoperationsandsomedesignhintsaregivenasfollows:ThebufferregisterBRisusedtoholdacharacterthathasbeensentviathesystembuswhilethatthecharacterisbeingtransferredtotheprinter.ThestatusregisterSRisusedfortwocontrolfunctions:SR7servesasareadyflagforsystembustransferstoBR(liketheprinterRDYsignalfortransfersfromPOCtotheprinter),andSR0isusedtoenableordisableinterruptrequestsfromPOC.IfSR0=1,thenPOCwillinterruptwhenitisreadytoreceiveacharacter(i.e.,whenSR7=1).IfSR0=0,thenPOCwillnotinterrupt.TheotherbitsofSRarenotusedandempty.ThetransferofacharactertoPOCviathesystembusproceedsasfollows.POCindicatesthatitisreadybysettingSR7.TheprocessorreadsSR(byexecutingapollingorinterruptserviceroutine)and,findingSR7=1,writesacharactertoBR.ThePOCclearsSR7whenitloadsthischaracterintoBRtoindicatethatanothercharactershouldnotbesentforthemoment.POCthenproceedstotransferthecharacterinBRtotheprinterbygeneratingapulseatTR.Theprocessor,inthemeantime,continuestofetchandTheDesignReportoftheparalleloutputcontroller(POC)4executeinstructions.IfitshouldhappentoreadSR,itwillfindSR7=0andhencewillnotattempttosendanothercharactertotheprinter.Whentheprinterisreadytoreceiveanothercharacter,POCsetsSR7.Thetransfercyclecannowrepeat.TheoverallconnectionFigure3TheoverallconnectionofthesimulatedprinterandPOCenteredintoQuartusIIintheformoftopmodulesymbolsTherearethreemodulesinthefigure:theSCPU,thePrintandthePOC.Accordingtothehintsinthedirection,weknowthatinordertosimulatethePOCbycomputer,asimulatedprinterisbeenwritten..SimulationResultsFigure4SimulationwaveformNameoftheportsandsignalinthesimulation:TheDesignReportoftheparalleloutputcontroller(POC)5CLK:theclockwaveinsideCS:theenablesignal.RESET:thesignaltoresetthePOC.IRQ:theinterruptsignalfromPOCtoCUP.ItispulledlowwhenSR(0)=SR(7)=1;RW:theinputsignalthatcontrolsthewritingofdatafromCPUtoPOC.ADR:theaddresschoicethedataontheDATAwritetotheSRortheBR.TR:apulsesignaltomaketheRDYbelow-level.RDY:theinputsignalsendingtoPOCthatmeansprinterisreadytoreceivemessage.DATA:theinputsignalofdatatobeused.PD:an8bitssignalfromPOCtoPrinter.Explanation:Fromthesimulationwaveform,wecanfigureoutthatthePOCandprinterisworkingcorrectly.Weshallanalyzetheresultsasfollowing:First,DATArepresentsthecharactersthatwillbetransferredtoPOCandfurthertotheprinter.‘0’meansnosignalisbeingtransferred.Whena‘20’comes,itshouldbeputforwardtotheBRinthePOC.Second,aRWsignalisathighlevel,thisdemonstratethatPOCisreadytoreceivedatafromCPU.WhentheADRis0ThenDATAisloadedintheBR.theADRis1theDATAisloadedintheBRAtthemeanwhile,aRDYsignalispulledhighandthatmeanstheprinterisreadytoreceivedatafromPOC.TRisaseriesofpulsestoshowthatthePOCisreadytotransferdatatotheprinter.(Itsfunctionisnotsorequiredandcompletedinthisexperiment.)WhatisimportantisthatwhenRDYisathighlevel,theIRQshouldalsobehightoensurethatinterruptisnotenabledduringtheprocesswhendataistransferredfromPOCtoprinter.Afterafewseconds,theprocessisfinishedandIRQisatlowleveltoenableinterrupt.AsaresultdatacanbetransferredwithinbusfromCPUtothePOC,andtheprintercandoitsjobatthesametime.Thisdemonstratestheprocessofparalleloutput.Finally,thefunctionofPOCcanbeperfectlyachieved.Discussiontotheresultsoftheexperiment1.Aretheresultsequaltothetheory?Answer:WecanseetheresultsofthesimulationinFigure4.Itshowsacorrectresultsrequiredbythetasksandthefunctioniswellaccordingtotheprinciples.2.Isthereanythingthatcanbe