慢速充电时钟芯片DS1302中英文资料

1DS1302TrickleChargeTimekeepingChip一、FEATURES1、Realtimeclockcountsseconds,minuteshours,dateofthemonth,month,dayoftheweek,andyearwithleapyearcompensationvalidupto2100.2、31x8RAMforscratchpaddatastorage.3、SerialI/Oforminimumpincount.4、2.0–5.5Vfulloperation.5、Useslessthan300nAat2.0V.6、Single–byteormultiple–byte(burstmode)datatransferforreadorwriteofclockorRAMdata.7、8–pinDIPoroptional8–pinSOICsforsurfacemount.8、Simple3–wireinterface.9、TTL–compatible(VCC=5V).10、Optionalindustrialtemperaturerange–40°Cto+85°C.11、DS1202compatible.二、PINASSIGNMENT三、PINDESCRIPTION①X1,X2：32.768kHzCrystalPins；②GND：Ground；③RST：Reset；④I/O：DataInput/Output；⑤SCLK：SerialClock；⑥VCC1,VCC2：PowerSupplyPins四、DESCRIPTIONTheDS1302TrickleChargeTimekeepingChipcontainsarealtimeclock/calendarand31bytesofstaticRAM.Itcommunicateswithamicroprocessorviaasimpleserialinterface.Therealtimeclock/calendarprovidesseconds,minutes,hours,day,date,month,andyearinformation.Theendofthemonthdateisautomaticallyadjustedformonthswithlessthan31days,includingcorrectionsforleapyear.Theclockoperatesineitherthe24–houror12–hourformatwithanAM/PMindicator.InterfacingtheDS1302withamicroprocessorissimplifiedbyusingsynchronousserialcommunication.Onlythreewiresarerequiredtocommunicatewiththeclock/RAM:(1)RST(Reset),(2)I/O(Dataline),and(3)SCLK(Serialclock).Datacanbetransferredtoandfromtheclock/RAM1byteatatimeorinaburstofupto31bytes.TheDS1302isdesignedtooperateonverylowpowerandretaindataandclockinformationonlessthan1microwatt.2TheDS1302isthesuccessortotheDS1202.InadditiontothebasictimekeepingfunctionsoftheDS1202,theDS1302hastheadditionalfeaturesofdualpowerpinsforprimaryandback–uppowersupplies,programmabletricklechargerforVCC1,andsevenadditionalbytesofscratchpadmemory.（1）、OPERATIONThemainelementsoftheSerialTimekeeperareshowninFigure1:shiftregister,controllogic,oscillator,realtimeclock,andRAM.DS1302BLOCKDIAGRAMFigure1（2）、SIGNALDESCRIPTIONS①VCC1：VCC1provideslowpoweroperationinsinglesupplyandbatteryoperatedsystemsaswellaslowpowerbatterybackup.Insystemsusingthetricklecharger,therechargeableenergysourceisconnectedtothispin.②VCC2：Vcc2istheprimarypowersupplypininadualsupplyconfiguration.VCC1isconnectedtoabackupsourcetomaintainthetimeanddateintheabsenceofprimarypower.③TheDS1302willoperatefromthelargerofVCC1orVCC2.WhenVCC2isgreaterthanVCC1+0.2V,VCC2willpowertheDS1302.WhenVCC2islessthanVCC1,VCC1willpowertheDS1302.④SCLK(SerialClockInput)–SCLKisusedtosynchronizedatamovementontheserialinterface.⑤I/O(DataInput/Output)–TheI/Opinisthebi-directionaldatapinforthe3-wireinterface.⑥RST(Reset)–Theresetsignalmustbeassertedhighduringareadorawrite.⑦X1,X2：Connectionsforastandard32.768kHzquartzcrystal.Theinternaloscillatorisdesignedforoperationwithacrystalhavingaspecifiedloadcapacitanceof6pF.（3）、COMMANDBYTEThecommandbyteisshowninFigure2.Eachdatatransferisinitiatedbyacommandbyte.TheMSB(Bit7)mustbealogic1.Ifitis0,writestotheDS1302willbedisabled.Bit63specifiesclock/calendardataiflogic0orRAMdataiflogic1.Bits1through5specifythedesignatedregisterstobeinputoroutput,andtheLSB(bit0)specifiesawriteoperation(input)iflogic0orreadoperation(output)iflogic1.ThecommandbyteisalwaysinputstartingwiththeLSB(bit0).ADDRESS/COMMANDBYTEFigure2（4）、RESETANDCLOCKCONTROLAlldatatransfersareinitiatedbydrivingtheRSTinputhigh.TheRSTinputservestwofunctions.First,RSTturnsonthecontrollogicwhichallowsaccesstotheshiftregisterfortheaddress/commandsequence.Second,theRSTsignalprovidesamethodofterminatingeithersinglebyteormultiplebytedatatransfer.Aclockcycleisasequenceofafallingedgefollowedbyarisingedge.Fordatainputs,datamustbevalidduringtherisingedgeoftheclockanddatabitsareoutputonthefallingedgeofclock.IftheRSTinputislowalldatatransferterminatesandtheI/Opingoestoahighimpedancestate.DatatransferisillustratedinFigure3.Atpower–up,RSTmustbealogic0untilVCC2.0volts.AlsoSCLKmustbeatalogic0whenRSTisdriventoalogic1state.DATATRANSFERSUMMARYFigure3（5）、DATAINPUTFollowingtheeightSCLKcyclesthatinputawritecommandbyte,adatabyteisinputontherisingedgeofthenexteightSCLKcycles.AdditionalSCLKcyclesareignoredshouldtheyinadvertentlyoccur.Dataisinputstartingwithbit0.（6）、DATAOUTPUTFollowingtheeightSCLKcyclesthatinputareadcommandbyte,adatabyteisoutputonthefallingedgeofthenexteightSCLKcycles.Notethatthefirstdatabittobetransmittedoccursonthefirstfallingedgeafterthelastbitofthecommandbyteiswritten.Additional4SCLKcyclesretransmitthedatabytesshouldtheyinadvertentlyoccursolongasRSTremainshigh.Thisoperationpermitscontinuousburstmodereadcapability.Also,theI/Opinistri–stateduponeachrisingedgeofSCLK.Dataisoutputstartingwithbit0.（7）、BURSTMODEBurstmodemaybespecifiedforeithertheclock/calendarortheRAMregistersbyaddressinglocation31decimal(address/commandbits1through5=logic1).Asbefore,bit6specifiesclockorRAMandbit0specifiesreadorwrite.Thereisnodatastoragecapacityatlocations9through31intheClock/CalendarRegistersorlocation31intheRAMregisters.Readsorwritesinburstmodestartwithbit0ofaddress0.Whenwritingtotheclockregistersintheburstmode,thefirsteightregistersmustbewritteninorderforthedatatobetransfe