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1.三与门libraryieee;useieee.std_logic_1164.all;entityyumenisport(a,b,c:instd_logic;f:outstd_logic);endyumen;architectureand3_1ofyumenisbeginf=aandbandc;endarchitectureand3_1;2.三八译码器libraryieee;useieee.std_logic_1164.all;entityjgisport(a,b,c,g1,g2a,g2b:instd_logic;y:outstd_logic_vector(7downto0));endentityjg;architecturert1ofjgissignalindata:std_logic_vector(2downto0);beginindata=c&b&a;process(indata,g1,g2a,g2b)isbeginif(g1='1'andg2a='0'andg2b='0')thencaseindataiswhen000=y=11111110;when001=y=11111101;when010=y=11111011;when011=y=11110111;when100=y=11101111;when101=y=11011111;when110=y=10111111;when111=y=01111111;whenothers=y=xxxxxxxx;endcase;elsey=11111111;endif;endprocess;endrt1;3.同步复位/置位、下降沿触发的d触发器ibraryieee;useieee.std_logic_1164.all;entityadffisport(clk,d,r,s:instd_logic;q:outstd_logic);endadff;architecturertlofadffissignalq_temp,qb_temp:std_logic;beginprocess(clk,r,s)beginif(clk'eventandclk='0')thenif(r='0'ands='1')thenq_temp='1';if(r='1'ands='0')thenq_temp='0';elseq_temp=d;endif;endif;endif;endprocess;q=q_temp;endrtl;4.异步复位/置位、上升沿触发的d发器ibraryieee;useieee.std_logic_1164.all;entityadffisport(clk,d,r,s:instd_logic;q:outstd_logic);endadff;architecturertlofadffissignalq_temp,qb_temp:std_logic;beginprocess(clk,r,s)beginif(r='0'ands='1')thenq_temp='1';elsif(r='1'ands='0')thenq_temp='0';elsif(clk'eventandclk='1')thenq_temp=d;endif;endprocess;q=q_temp;endrtl;5.四分频器ibraryieee;useieee.std_logic_1164.all;entityoneisport(clk1:instd_logic;clk4:outstd_logic);endone;architectureone1ofoneissignaldata1:integerrange0to10;signalq1:std_logic;beginprocess(clk1)beginifrising_edge(clk1)thenif(data1=1)thendata1=0;q1=notq1;elsedata1=data1+1;endif;endif;clk4=q1;endprocess;endarchitectureone1;6.四选一libraryieee;useieee.std_logic_1164.all;entitymux4isport(input:instd_logic_vector(3downto0);a,b:instd_logic;y:outstd_logic);endmux4;architecturertlofmux4issignalsel:std_logic_vector(1downto0);beginsel=b&a;process(input,sel)beginif(sel=00)theny=input(0);elsif(sel=01)theny=input(1);elsif(sel=10)theny=input(2);elsey=input(3);endif;endprocess;endrtl;7.五分频器useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;useieee.std_logic_arith.all;entityfenpin5isport(rst,clkin:instd_logic;clkout:outstd_logic);endfenpin5;architecturertloffenpin5issignalcount1,count2:std_logic_vector(7downto0);signaltmp,tmp1,tmp2:std_logic;begintmp=tmp1andtmp2;clkout=tmpxortmp1;process(clkin,rst)beginifrst='1'thencount1=00000000;tmp1='0';elsifclkin'eventandclkin='1'thenifcount1=00000100thencount1=00000000;elsecount1=count1+1;ifcount100000010thentmp1='0';elsetmp1='1';endif;endif;endif;endprocess;endrtl;8.moore状态机libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entitymooreisport(rst,clk,x:instd_logic;op:outstd_logic);endmoore;architectureaofmooreistypestateis(s0,s1,s2,s3);signalst:state;beginstate_comp:process(rst,clk)beginifrst='1'thenst=s0;elsifrising_edge(clk)thencasestiswhens0=ifx='0'thenst=s0;elsest=s1;endif;op='1';whens1=ifx='0'thenst=s3;elsest=s2;endif;op='1';whens2=ifx='0'thenst=s2;elsest=s3;endif;op='1';whens3=ifx='0'thenst=s3;elsest=s0;endif;op='0';endcase;endif;endprocessstate_comp;enda;9.mealy状态机libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entitymealyisport(rst,clk,x:instd_logic;op:outstd_logic);endmealy;architectureaofmealyistypestateis(s0,s1,s2,s3);signalst:state;beginstate_comp:process(rst,clk)beginifrst='1'thenst=s0;elsifrising_edge(clk)thencasestiswhens0=ifx='0'thenst=s0;op='0';elsest=s1;op='1';endif;whens1=ifx='0'thenst=s3;op='1';elsest=s2;op='1';endif;whens2=ifx='0'thenst=s2;op='0';elsest=s3;op='1';endif;whens3=ifx='0'thenst=s3;op='0';elsest=s0;op='0';endif;endcase;endif;endprocessstate_comp;enda10.全加器libraryieee;useieee.std_logic_1164.all;entityfull_adderisport(a,b,cin:instd_logic;s,co:outstd_logic);endfull_adder;architecturefull1offull_adderissignaltmp1,tmp2,tmp3:std_logic;begintmp1=axorb;tmp2=aandb;tmp3=tmp1andcin;s=tmp1xorcin;co=tmp2ortmp3;endfull1;11.同步12进制计数器libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitycount12enisport(clk,clr,en:instd_logic;qa,qb,qc,qd:outstd_logic);endcount12en;architecturertlofcount12enissignalcount_4:std_logic_vector(3downto0);beginqa=count_4(0);qb=count_4(1);qc=count_4(2);qd=count_4(3);process(clr,clk)beginif(clr='1')thencount_4=0000;elsif(clk'eventandclk='1')thenif(en='1')thenif(count_4=1011)thencount_4=0000;elsecount_4=count_4+'1';endif;endif;endif;endprocess;endrtl;12.优先编码器libraryieee;useieee.std_logic_1164.all;entitypriority_encoderisport(input:instd_logic_vector(7downto0);y:outstd_logic_vector(2downto0));endpriority_encoder;architecturertlofpriority_encoderisbeginp1:process(input)beginif(input(0)='0')theny=111;elsif(input(1)='0')theny=110;elsif(input(2)='0')theny=101;elsif(input(3)='0')theny=100;elsif(input(4)='0')theny=011;elsif(input(5)='0')theny=010;elsif(input(6)='0')theny=001;elsey=00