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KONXINKONXIN5VHDL955VHDL(SequentialStatements)(ConcurrentStatements)VHDL()(Process)(Function)(Procedure)VHDLVHDLVHDLVHDLVHDLhhhhhh§5.1KONXINKONXIN5VHDL96VHDL5.1.1==VHDL()()()DVHDL(9):==5-15-1SIGNALs1,s2:STD_LOGIC;SIGNALsvec:STD_LOGIC_VECTOR(0TO7);...PROCESS(s1,s2)VARIABLEv1,v2:STD_LOGICBEGINKONXINKONXIN5VHDL97v1:='1';--v11v2:='1';--v21s1='1';--s11s2='1';--s2--svec(0)=v1;--v11svec(0)svec(1)=v2;--v21svec(1)svec(2)=s1;--s11svec(2)svec(3)=s2;--s2'0'svec(3)v1:='0';--v10v2:='0';--v20s2='0';--s2--'0''1'svec(4)=v1;--v10svec(4)svec(5)=v2;--v20svec(5)svec(6)=s1;--s11svec(6)svec(7)=s2;--s20svec(7)ENDPROCESS;5.1.21.5-25-2VARIABLEabSTD_LOGIC;SIGNALc1:STD_LOGIC_VECTOR(1TO4);a:='1'b:='0'c1:=1100abc12.()()5-35-3KONXINKONXIN5VHDL98SIGNALabSTD_LOGIC_VECTOR(0TO3);SIGNALiINTEGERRANGE0TO3;SIGNALyzSTD_LOGIC;...--a=1010;b=1000;a(I)=y;--b(3)=z;--3.(1TO(DOWNTO)2)TODOWNTO5-45-4VARIABLEabSTD_LOGIC_VECTOR(1TO4);a(1TO2):=10--a(1):='1'a(2):='0'a(1To4):=10114.5-5SIGNALa,b,c,dSTD_LOGICSIGNALsSTD_LOGIC_VECTOR(1TO4);...VARIABLEe,fSTD_LOGICVARIABLEgSTD_LOGIC_VECTOR(1TO2);VARIABLEh:STD_LOGIC_VECTOR(1TO4);s=('0''1''0''0')(a,b,c,d)=s;--...--(3=e,4=f2=g(1)1=g(2)):=h--a='0'b='1'c='0'd='0'g(2)=h(1)g(1)=h(2)e=h(3)f=h(4)KONXINKONXIN5VHDL99§5.2hIFhCASEhLOOPhNEXThEXIT5.2.1IFIFIFIFThen--IFENDIFIFThen--IFELSEENDIFIFThen--IFELSIFThen...ELSEENDIFIFBOOLEANIFTRUEFALSEIF(TRUE)(THEN)ENDIFIF(FALSE)IFIF5-6KONXINKONXIN5VHDL1005-6k1:IF(ab)THENoutput='1';ENDIFk1;k1(ab)TRUEoutput1IFIFFALSEENDIFELSEIFIFIF25-7FUNCTIONand_func(x,y:INBIT)RETURNBITISBEGINIFx='1'ANDy='1'THENRETURN'1';ELSERETURN'0';ENDIFENDand_func;IFBOOLEAN5-85-8LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYcontrol_stmtsISPORT(a,b,c:INBOOLEAN;output:OUTBOOLEAN);ENDcontrol_stmts;ARCHITECTUREexampleOFcontrol_stmtsISBEGINPROCESS(a,b,c)VARIABLEn:BOOLEAN;BEGINIFaTHENn:=b;ELSEn:=c;ENDIF;output=n;ENDPROCESS;ENDexample;5-85-1aKONXINKONXIN5VHDL101IFELSIF()5-221VHDL5-9p1p25-9SIGNALa,b,c,p1,p2,z:BIT;...IF(p1='1')THENz=a;--(p1='1')ELSIF(p2='0')THENz=b;--(p1='0')AND(p2='0')ELSEz=c;--(p1='0')AND(p2='1')ENDIF;5-9IFIF-THEN-ELSIF5-108-35-15-10LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYcoderISPORT(din:INSTD_LOGIC_VECTOR(0TO7);output:OUTSTD_LOGIC_VECTOR(0TO2));ENDcoder;ARCHITECTUREbehavOFcoderISSIGNALSINT:STD_LOGIC_VECTOR(4DOWNTO0);BEGINPROCESS(din)BEGINIF(din(7)='0')THENoutput=000;--(din(7)='0')ELSIF(din(6)='0')THENoutput=100;--(din(7)='1')AND(din(6)='0')ELSIF(din(5)='0')THENcaoutputb5-15-85-221KONXINKONXIN5VHDL102output=010;--(din(7)='1')AND(din(6)='1')AND(din(5)='0')ELSIF(din(4)='0')THENoutput=110;ELSIF(din(3)='0')THENoutput=001;ELSIF(din(2)='0')THENoutput=101;ELSIF(din(1)='0')THENoutput=011;ELSEoutput=111;ENDIFENDPROCESSENDbehav;5-18-3din0din1din2din3din4din5din6din7output0output1output2xxxxxxx0000xxxxxx01100xxxxx011010xxxx0111110xxx01111001xx011111101x011111101101111111111xVHDL5-10output=111(in(7)='1')AND(in(6)='1')AND(in(5)='1')AND(in(4)='1')AND(in(3)='1')AND(in(2)='1')AND(in(1)='1')AND(in(0)='0')5-15.2.2CASECASECASECASEISWhen=When=...ENDCASECASEKONXINKONXIN5VHDL103CASE(=THEN)[|]h4h(2TO4)234h3│535hCASE(1)(2)CASEOTHERSOTHERSOTHERSSTD_LOGICSTD_LOGIC_VECTOR10ZX(3)CASE(4)CASECASE5-11CASE41VHDL5-11LIBRARYIEEEUSEIEEE.STD_LOGIC_1164.ALLENTITYmux41ISPORT(s1,s2:INSTD_LOGIC;a,b,c,d:INSTD_LOGIC;z:OUTSTD_LOGIC);ENDENTITYmux41ARCHITECTUREactivOFmux41ISSIGNALs:STD_LOGIC_VECTOR(1DOWNTO0);BEGINs=s1&s2;PROCESS(s,a,b,c,d)–-ss1s2BEGINCASEsISWHEN00=z=a;WHEN01=z=b;KONXINKONXIN5VHDL104WHEN10=z=c;WHEN11=z=d;WHENOTHERS=z='X';--XENDCASEENDPROCESSEndactiv5-11STD_LOGIC_VECTORsVHDL00011011STD_LOGIC5-3WHENOTHERS=z='X'XSTD_LOGIC5-1241IFCASE4415-12LIBRARYIEEEUSEIEEE.STD_LOGIC_1164.ALLENTITYmux41ISPORT(s4s3,s2s1:INSTD_LOGIC;z4z3,z2z1:OUTSTD_LOGIC);ENDmux41ARCHITECTUREactivOFmux41ISSIGNALsel:INTEGERRANGE0TO15;BEGINPROCESS(sels4s3s2s1)BEGINsel=0;--IF(s1='1')THENsel=sel+1;ELSIF(s2='1')THENsel=sel+2;ELSIF(s3='1')THENsel=sel+4;ELSIF(s4='1')THENsel=sel+8;ELSENULL;--ENDIF;z1='0';z2='0';z3='0';z4='0';--CASEselISWHEN0=z1='1';--sel=0WHEN1│3=z2='1';--sel13WHEN4To7│2=z3='1';--sel24567WHENOTHERS=z4='1';--sel815ENDCASEABCDS0S1s1s2dczba5-341KONXINKONXIN5VHDL105ENDPROCESSENDactiv5-12IF-THEN-ELSIFs4s3s2s14sel5-13CASE5-13SIGNALvalue:INTEGERRANGE0TO15;SIGNALout1:STD_LOGIC;...CASEvalueIS--WHENENDCASE...CASEvalueISWHEN0=out1='1';--value215WHEN1=out1='0';ENDCASE...CASEvalueISWHEN0TO10=out1='1';--510WHEN5TO15=out1='0';ENDCASEIFCASECASEIFCASECASEIFCASEIFIF-THEN-ELSLF()CASE5-14VHDLopcodeCASEIF-THEN5-14LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYaluISPORT(a,b:INSTD_LOGIC_VECTOR(7DOWNTO0);opcode:INSTD_LOGIC_VECTOR(1DOWNTO0);result:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDalu;ARCHITECTUREbehaveOFaluISCONSTANTplus:STD_LOGIC_VECTOR(1DOWNTO0):=b00;CONSTANTminus:STD_LOGIC_VECTOR(1DOWNTO0):=b01;CONSTANTequal:STD_LOGIC_VECTOR(1DOWNTO0):=b10;KONXINKONXIN5VHDL106CONSTANTnot_equal:STD_LOGIC_VECTOR(1DOWNTO0):=b11;BEGINPROCESS(opcode,a,b)BEGINCASEopcodeISWHENplus=result=a+b;--