Cell-Characterization

AccuCellIntroductiontoCellCharacterization2OverviewßObjectiveofCellCharacterizationßDigitalDesignToolsthatUseStandardCellModelsßInputDataFilesRequiredbyDigitalDesignToolsßTypesofStandardCellLibrariesßInputViewsofCircuits–BridgingAnalogandDigitalßCellLibraryAttributesßCellLibraryModelQualityßSynopsysLibertyFormat(.lib)ßCharacterizationofGatesßCharacterizationofSequentialCircuits3SummarySlideßObjectiveofCellCharacterizationßDigitalDesignToolsThatUseStandardCellModelsßInputDataFilesRequiredbyDigitalDesignTools(GeneratedbyAccuCell)ßInputDataFilesRequiredbyDigitalDesignTools(GeneratedbyOtherTools)ßTypesofStandardCellLibrariesßDigitalCircuitRepresentation–InverterßAnalogCircuitDescription-InverterßInputViewsofCircuitsBridgingAnalogandDigitalßStaticTimingAnalysisUseofLibertyFormatßCellLibraryAttributesßMeasurementsßCellLibraryModelQualityßLiberty.libFileStructureßOperatingConditionsßCellAttributesin.libFileßDatasheetViewofAND2ßPinAttributesßSettingOutputLoadLimitsßDelayModelingConceptsßTotalDelayEquationßSlopeDelayßSlewModelingßIntrinsicandTransitionDelaysßConnectDelayßInterconnectDelayßTimingArcsßCombinationalTimingArcsßSequentialTimingArcsßTimingArcsBetweenSingleandMultiplePinsßThree-StateTimingArcsßEdge-SensitiveTimingArcsßPresetArcsßClearArcsßDefiningDelayArcsWithLookupTablesßDefiningLookupTableTemplatesßAssigningValuestoLookupTablesßTimingConstraintsßSetupandHoldConstraintsßNonSequentialSetupandHoldConstraintsßRecoveryTimingConstraintsßRemovalTimingConstraintsß.libofStateTableFlipFlopß.libofTypeffDFlipFlopßComponentsofPowerDissipationßPowerModelingßStateDependentLeakagePowerßModelingInternalPowerLookupTablesßInternalPowerCalculationsßClockPinPowerßOutputPinPowerßPowerLookupTablesDescriptions1D,2D,3DßInternalPowerTableforCellOutputßCalculatingSwitchingPowerßSwitchingPowerCalculations4ObjectiveofCellCharacterizationßCreateasetofhighqualitymodelsofastandardcelllibrarythataccuratelyandefficientlymodelcellbehavior.Thissetofmodelsareusedbyseveraldifferentdigitaldesigntoolsfordifferentpurposes.5DigitalDesignToolsThatUseStandardCellModelsßSynthesisToolsßPlaceandRoutingSystemsßHighlevelDesignLanguage(HDL)Simulators(VerilogandVHDL)ßFloorplanningToolsßPhysicalPlacementtoolsßStaticTimingAnalysis(STA)toolsßPowerAnalysistoolsßFormalVerificationtoolsßAutomaticTestProgramGeneration(ATPG)toolsßLibraryCompiler6InputDataFilesRequiredbyDigitalDesignTools(GeneratedbyAccuCell)ß.libTechnologylibrarysourcefilesß.vGeneratedVerilogsimulationlibrariesß.vhdGeneratedVHDLsimulationlibrariesßatpg.libATPGlibraryß.tbenchVerilogtestbenchtocompareSPICEtoVerilogwithsamestimulusß.htmlHTMLdatasheet7InputDataFilesRequiredbyDigitalDesignTools(GeneratedbyOtherTools)ß.dbCompiledtechnologylibrariesinSynopsysinternaldatabaseformatßSynopsysMilkywayFiles-AbstractsorBoundingBoxesßCadenceEncounterFiles-AbstractsorBoundingBoxesß.LEFß.DEFßGDS8TypesofStandardCellLibrariesßThereareoftenseveralcelllibrariespersemiprocessthattypicallycontain100to1,000cellsincluding:ßFunctionsßGates–inverter,AND,NAND,NOR,XOR,AOI,OAIßFlops–Flipflops(D,RS,JK),Latches,ScanFlops,GatedFlopsßI/OCells–Inputpads,Outputpads,BidirectionalPads,ComplexßProcessOptionsßMasklayeroptions,gateshrinks,#ofmetals,specialdiffusions,thickmetal,multipleoxidesßCellOptionsßDrivestrengths,sets,resets,scans,substrateties,antennadiodesßOptimizedforAddressingTradeoffsBetweenßHighspeed,highdensity,lowpower,lowleakage,lowvoltage,lownoiseßCellLibrariesareProducedbyFoundries,IPVendors,FablessandIDMs9DigitalCircuitRepresentation–InverterIEEE-1164VerilogLogicStatesStrengthStateValueUUninitializedDrivenXUnknownDriven0LowDriven1HighZHighimpedanceResistiveWWeakXResistiveLWeak0ResistiveHWeak1--Don’tcareVerilogLanguageDescriptionofInverternoti1(out,in);//basicinverternot#(5,3)i1(out,in);//Rise=5ns,Fall=3nsInverterRise/FallDiagram10AnalogCircuitDescription-InverterSchematicNetlistTransistorInverterSchematicSchematicNetlistwithParasitics*svc_inv.schM3yagndgndnmosL=0.35uW=4.0uM2yavddvddpmosL=0.35uW=4.0u.END*svc_inv.schM3yagndgndnmosL=0.35uW=4.0uM2yavddvddpmosL=0.35uW=4.0uC1…..C2…..C3…...END11InputViewsofCircuitsBridgingAnalogandDigitalßTimingbackannotationforVerilogsimulator(gate,behavioral)ModelmustworkinVerilog-XL,VCS,NCsim,Modelsim,SILOSßMethodologyhaslimitationsonaccuracy(loadbasedonly)ßSTAispreferredmethodology12StaticTimingAnalysisUseofLibertyFormatßInastandaloneflow,STAoperatesindependentlyofcharacterizationreadingbothaVerilognetlistandmultipletiminglibrariesinLibertyformat.ItcanalsoreadinterconnectparasiticdatainSPForSDFformats.13CellLibraryAttributesßPinTypesßdirectionßfunctionßLoadsßCapacitiveßActiveßFanoutandwireloadsßStimulusßPWLforslopeßActivedriversßIndexesßLoadßInputslopepin(A){direction:output;function:X+Y;}lu_table_template(wire_delay_table_template){variable_1:fanout_number;variable_2:fanout_pin_capacitance;variable_3:driver_slew;index_1(1.0,3.0);index_2(0.12,4.24);index_3(0.1,2.7,3.12);}lu_table_template(trans_template){variable_1:total_output_net_capacitance;index_1(0.0,1.5,2.0,2.5);}wire_load(05x05){r