SPI完整程序

SPI接口源程序modulesimple_spi_top(//8bitWISHBONEbusslaveinterfaceinputwireclk_i,//clockinputwirerst_i,//reset(asynchronousactivelow)inputwirecyc_i,//cycleinputwirestb_i,//strobeinputwire[1:0]adr_i,//addressinputwirewe_i,//writeenableinputwire[7:0]dat_i,//datainputoutputreg[7:0]dat_o,//dataoutputoutputregack_o,//normalbusterminationoutputreginta_o,//interruptoutput//SPIportoutputregsck_o,//serialclockoutputoutputwiremosi_o,//MasterOutSlaveINinputwiremiso_i//MasterInSlaveOut);////Modulebody//reg[7:0]spcr;//SerialPeripheralControlRegister('HC11naming)wire[7:0]spsr;//SerialPeripheralStatusregister('HC11naming)reg[7:0]sper;//SerialPeripheralExtensionregisterreg[7:0]treg,rreg;//Transmit/Receiveregister//fifosignalswire[7:0]rfdout;regwfre,rfwe;wirerfre,rffull,rfempty;wire[7:0]wfdout;wirewfwe,wffull,wfempty;//miscsignalswiretirq;//transferinterrupt(selectednumberoftransfersdone)wirewfov;//writefifooverrun(writingwhilefifofull)reg[1:0]state;//statemachinestatereg[2:0]bcnt;////Wishboneinterfacewirewb_acc=cyc_i&stb_i;//WISHBONEaccesswirewb_wr=wb_acc&we_i;//WISHBONEwriteaccess//dat_ialways@(posedgeclk_iornegedgerst_i)if(~rst_i)beginspcr=#18'h10;//setmasterbitsper=#18'h00;endelseif(wb_wr)beginif(adr_i==2'b00)spcr=#1dat_i|8'h10;//alwayssetmasterbitif(adr_i==2'b11)sper=#1dat_i;end//writefifoassignwfwe=wb_acc&(adr_i==2'b10)&ack_o&we_i;assignwfov=wfwe&wffull;//dat_oalways@(posedgeclk_i)case(adr_i)//synopsysfull_caseparallel_case2'b00:dat_o=#1spcr;2'b01:dat_o=#1spsr;2'b10:dat_o=#1rfdout;2'b11:dat_o=#1sper;endcase//readfifoassignrfre=wb_acc&(adr_i==2'b10)&ack_o&~we_i;//ack_oalways@(posedgeclk_iornegedgerst_i)if(~rst_i)ack_o=#11'b0;elseack_o=#1wb_acc&!ack_o;//decodeSerialPeripheralControlRegisterwirespie=spcr[7];//Interruptenablebitwirespe=spcr[6];//SystemEnablebitwiredwom=spcr[5];//PortDWired-ORModeBitwiremstr=spcr[4];//MasterModeSelectBitwirecpol=spcr[3];//ClockPolarityBitwirecpha=spcr[2];//ClockPhaseBitwire[1:0]spr=spcr[1:0];//ClockRateSelectBits//decodeSerialPeripheralExtensionRegisterwire[1:0]icnt=sper[7:6];//interruptontransfercountwire[1:0]spre=sper[1:0];//extendedclockrateselectwire[3:0]espr={spre,spr};//generatestatusregisterwirewr_spsr=wb_wr&(adr_i==2'b01);regspif;always@(posedgeclk_i)if(~spe)spif=#11'b0;elsespif=#1(tirq|spif)&~(wr_spsr&dat_i[7]);regwcol;always@(posedgeclk_i)if(~spe)wcol=#11'b0;elsewcol=#1(wfov|wcol)&~(wr_spsr&dat_i[6]);assignspsr[7]=spif;assignspsr[6]=wcol;assignspsr[5:4]=2'b00;assignspsr[3]=wffull;assignspsr[2]=wfempty;assignspsr[1]=rffull;assignspsr[0]=rfempty;//generateIRQoutput(inta_o)always@(posedgeclk_i)inta_o=#1spif&spie;////hookupread/writebufferfifofifo4#(8)rfifo(.clk(clk_i),.rst(rst_i),.clr(~spe),.din(treg),.we(rfwe),.dout(rfdout),.re(rfre),.full(rffull),.empty(rfempty)),wfifo(.clk(clk_i),.rst(rst_i),.clr(~spe),.din(dat_i),.we(wfwe),.dout(wfdout),.re(wfre),.full(wffull),.empty(wfempty));////generateclkdividerreg[11:0]clkcnt;always@(posedgeclk_i)if(spe&(|clkcnt&|state))clkcnt=#1clkcnt-11'h1;elsecase(espr)//synopsysfull_caseparallel_case4'b0000:clkcnt=#112'h0;//2--originalM68HC11coding4'b0001:clkcnt=#112'h1;//4--originalM68HC11coding4'b0010:clkcnt=#112'h3;//16--originalM68HC11coding4'b0011:clkcnt=#112'hf;//32--originalM68HC11coding4'b0100:clkcnt=#112'h1f;//84'b0101:clkcnt=#112'h7;//644'b0110:clkcnt=#112'h3f;//1284'b0111:clkcnt=#112'h7f;//2564'b1000:clkcnt=#112'hff;//5124'b1001:clkcnt=#112'h1ff;//10244'b1010:clkcnt=#112'h3ff;//20484'b1011:clkcnt=#112'h7ff;//4096endcase//generateclockenablesignalwireena=~|clkcnt;//transferstatemachinealways@(posedgeclk_i)if(~spe)beginstate=#12'b00;//idlebcnt=#13'h0;treg=#18'h00;wfre=#11'b0;rfwe=#11'b0;sck_o=#11'b0;endelsebeginwfre=#11'b0;rfwe=#11'b0;case(state)//synopsysfull_caseparallel_case2'b00://idlestatebeginbcnt=#13'h7;//settransfercountertreg=#1wfdout;//loadtransferregistersck_o=#1cpol;//setsckif(~wfempty)beginwfre=#11'b1;state=#12'b01;if(cpha)sck_o=#1~sck_o;endend2'b01://clock-phase2,nextdataif(ena)beginsck_o=#1~sck_o;state=#12'b11;end2'b11://clockphase1if(ena)begintreg=#1{treg[6:0],miso_i};bcnt=#1bcnt-3'h1;if(~|bcnt)beginstate=#12'b00;sck_o=#1cpol;rfwe=#11'b1;endelsebeginstate=#12'b01;sck_o=#1~sck_o;endend2'b10:state=#12'b00;endcaseendassignmosi_o=treg[7];//countnumberoftransfers(forinterruptgeneration)reg[1:0]tcnt;//transfercountalways@(posedgeclk_i)if(~spe)tcnt=#1icnt;elseif(rfwe)//rfwegetsassertedwhenallbitshavebeentransferedif(|tcnt)tcnt=#1tcnt-2'h1;elsetcnt=#1icnt;assigntirq=~|tcnt&rfwe;endmodule*******************************************************************************//4entrydeepfastfifomodulefifo4(clk,rst,clr,din,we,dout,re,full,empty);parameterdw=8;inputclk,rst;inputclr;input[dw:1]din;inputwe;output[dw:1]dout;inputre;outputfull,empty;reg[dw:1]mem[0:3];reg[1:0]wp;reg[1:0]rp;wire[1:0]wp_p1;wire[1:0]wp_p2;wire[1:0]rp_p1;wirefull,empty;reggb;always@(posedgeclkornegedgerst)if(!rst)wp=#12'h0;elseif(clr)wp=#12'h0;elseif(we)wp=#1wp_p1;assignwp_p1=wp+2'h1;assignwp_p2=wp+2'h2;always@(posedgeclkor