RTL General Coding Style andCoding Style for Synth

IntroductiontoSiliconIPDesign/Supplement1-2RTLGeneralCodingStyleandCodingStyleforSynthesisIntroductiontoSiliconIPDesign/Supplement1-2Topics™BasicGoals™Template™GeneralCodingStyles™NamingConvention™Comments™CircuitCodingGuidelines™KnowWhattobeTranslated™DesignWare™QoSandQoRIntroductiontoSiliconIPDesign/Supplement1-2BasicGoals™Verilog,likeotherprogramminglanguages,offersmanyfeaturesthatallowforthecreationofverycomplexstructures.™However,thesefeatures,ifusedpoorly,cancreatehardwarethat,whilecorrect,isoverlycomplexordifficulttounderstandanddebug.™CodeshouldbeorganizedinawaythatevennoviceVerilogprogrammersareabletopickitupandunderstanditsfunction.™Basicgoal=simpleandregularŠUsesimpleconstructs,andsimpleclockingschemes.ŠConsistentcodingstyle,consistentnamingandstatemachines.ŠRegularpartitioningschemeŠEasytounderstandbycommentsandmeaningfulnames.Nohardcodednumber.IntroductiontoSiliconIPDesign/Supplement1-2OrganizeYourDesignWorkspace™Defineafilenamingconventionanddocumentit.™CreateadirectorystructureforstoringHDLsource,simulationlibraries,synthesisscriptsandsynthesisdbs.designhdlvhdlverilog.vhd.vanalyzed.mra.sim.synsynScripts.con.scr.setup_dcDB.dbDW_cacheLog.log.rptNetlist.edif.v.vhdSimInvokeDesignCompilerFromthisDirectory!synopsys_dc.setupIntroductiontoSiliconIPDesign/Supplement1-2CodeTemplate/*********************************************************///MODULE:CODETEMPLATE////FILENAME:template.v//VERSION:1.0//DATE:January1,1999//AUTHOR:Jinn-ShyanWang////CODETYPE:RTLorBehavioralLevel////DESCRIPTION:ThistemplateisusedtohaveacodingstandardforeachVerilogfunctioninyourhomeworkandproject////MODIFICATIONHISTORY://DateDescription//03/04/2003/*********************************************************///DEFINES//TOPMODULE//INPUTS//OUTPUTS//INOUTS//SIGNALDECLARATIONS//PARAMETERS//ASSIGNSTATEMENTS//MAINCODEIntroductiontoSiliconIPDesign/Supplement1-2GeneralCodingStyles(1)™Includeheadersinsourcefiles.ŠFilename,authors,descriptionoffunctions,date,modificationhistory,…™Modulenamesameasfilename™Usecomments™Indentation™PortOrderingŠDeclareoneportperlineandfollowbyacommentŠDeclareportinthefollowingorder¾Inputs:Clocks,reset,enables,controlsignals,data,andaddress¾Outputs:clocks,resets,enables,controlsignals,dataIntroductiontoSiliconIPDesign/Supplement1-2GeneralCodingStyles(2)™PortMapsŠUsenamedassociationratherthanpositionassociation.¾.a(in1),.b(in2),.ci(carry_in),.sum(sum),.co(carry_out)ŠLeaveablanklinebetweentheI/Oportstoimprovethereadability.™Usefunctionsasmuchaspossibletosavethecodinglines.™UseLoopsandarrays.™Usemeaningfullabels.™Donotusehard-codednumericvalues.IntroductiontoSiliconIPDesign/Supplement1-2NamingConvention™Documentthenamingconvention.™Lowercaseletterforsignalnames,variablenamesandportnames.™Uppercaseforconstantsanduser-definedtypes.™MeaningfulnamesforsignalsEx:ram_addr(notra)™Useshortbutdescriptivenames.™clkforclocksignals.Ex:clk1,clk2™Activelowsignals-endwith_n™rstforreset.rst_nforresetwithactivelow.™Usewire[n:0]insteadof[0:n];™UsethesameorsimilarnameforthoseconnectedtogetherEx:assigna=a1;IntroductiontoSiliconIPDesign/Supplement1-2Comments(1)™Commentsshouldbemeaningful.™ExampleBadexamplei=i+1;//iisincrementedBetteri=i+1;//IncrementthearrayindexEvenbetteri=i+1;//Sincethiselementofthearraydidnotmeet//ourcriteria,incrementtheindextoexamine//thenextelementIntroductiontoSiliconIPDesign/Supplement1-2Comments(2)™Groupsofsignalnamesandcommentsreadmuchbetteriftheyarelinedupexactlyatthesameplaceatthepage.™Example//INPUTSinputreset_n;//Activelowresetinput[‘FIFO_WIDTH-1:0]data_in;//DatainputtoFIFOinputread_n//ReadFIFO(activelow)inputwrite_n//WriteFIFO(activelow)//OUTPUTSoutput[‘FIFO_WIDTH-1:0]data_out;//FIFOdataoutputoutputfull//FIFOisfulloutputempty//FIFOisemptyoutputhalf//FIFOishalffullormoreIntroductiontoSiliconIPDesign/Supplement1-2Comments(3)™Eachsectionofcodeshouldbeginwithageneralcommentdescribingwhatitisdoing.™Foreachblockthatincludesmultiplechoicesofexecution,suchasifstatements,casestatements,andfork-joinstatements,eachalternativeshouldhaveitsowncomment.™Example//DescribeTHEALWAYSBLOCK://ThisblockcontainsalldevicesaffectedbywriteinputAlways@(negedgewrite_n)begin//DESCRIBETHEIFSTATEMENT://CheckforFIFOoverflowif(counter=‘FIFO_DEPTH)begin//COMMENTFORTHISBRANCHISNOTNEEDED//BECAUSETHE$DISPLAYSTATEMENTISEXPLANATORY$display(“\nERRORattime%0t:”,$time);$display(“FIFOOverflow\n”);endelasebegin//COMMENTFORTHISBRANCH://Storethedatafifo_mem[wr_pointer]=#’DELdata_in;endendIntroductiontoSiliconIPDesign/Supplement1-2Comments(4)™Theendofeachmoduleshouldhaveacommentattachedthatgivesthenameofthemodule.™Examplemodulestate_machine(clock,reset_n,wr,rd,ready,out_en,write_en,ack);...endmodule//state_machineIntroductiontoSiliconIPDesign/Supplement1-2CircuitCodingGuidelines--(1)PartitionforSynthesis™Followthefollowingrecommendationstoachievebestsynthesisresultsandreductionincompiletime.1)Partitionfordesignreuse.2)Avoidasynchronouslogic.3)Minimizeunnecessaryhierarchy.4)Keeprelatedcombinationallogicinthesamemodule.5)Separatemodulesaccordingtoth