基于VHDL的数字时钟课程设计

数字时钟设计1.设计要求(1)能显示周、时、分、秒，精确到0.1秒(2)可自行设置时间(3)可设置闹铃，并且对闹铃时间长短可控制2.设计分析（1）根据题目要求可分解为正常计时、时间设置和闹铃设置三大模块（2）正常计时模块可分解为周、时、分、秒等子模块（3）时间设置模块分别进行秒置数、分置数、时置数和周置数（4）闹铃设置模块分解为闹钟判定和闹铃时长设定3.设计结构图时间重置正常计数闹钟设定数字显示数字钟4.设计流程图否是是否开始重置时间？秒重置分重置时重置正常计时正常计时时间重置？是--Second1(秒计数6进制和10进制)Libraryieee;Useieee.std_logic_1164.all;Useieee.std_logic_unsigned.all;Entitysecond1isPort(clks,set:instd_logic;s1,s0:instd_logic_vector(3downto0);Secs,Secg:bufferstd_logic_vector(3downto0);cout1:outstd_logic);Endsecond1;Architectureaofsecond1isBeginProcess(clks,set)variabless,sg:std_logic_vector(3downto0);--(ss:秒十位；sg秒个位)variableco:std_logic;BeginIfset='1'thenss:=s1;sg:=s0;设置闹钟？时设定分设定时刻到达？响铃时间显示Elsifclks'eventandclks='1'thenifss=0101andsg=1001thenss:=0000;sg:=0000;co:='1';elsifsg1001thensg:=sg+1;co:='0';elsifsg=1001thensg:=0000;ss:=ss+1;co:='0';endif;endif;cout1=co;--（进位信号）Secs=ss;Secg=sg;endprocess;Enda;仿真波形图：--Min1（分计数器6进制和10进制alm实现整点报时）Libraryieee;Useieee.std_logic_1164.all;Useieee.std_logic_unsigned.all;Entitymin1isPort(clkm,set:instd_logic;m1:instd_logic_vector(3downto0);m0:instd_logic_vector(3downto0);mins,ming:outstd_logic_vector(3downto0);enmin,alarm:outstd_logic);End;Architectureaofmin1isBeginProcess(clkm,set)variablems,mg:std_logic_vector(3downto0);variableso,alm:std_logic;Beginifset='0'thenms:=m1;mg:=m0;Elsifclkm'eventandclkm='1'thenifms=0101andmg=1001thenms:=0000;mg:=0000;so:='1';alm:='1';elsifmg1001thenmg:=mg+1;so:='0';alm:='0';elsifmg=1001thenmg:=0000;ms:=ms+1;so:='0';alm:='0';endif;endif;alarm=alm;enmin=so;mins=ms;ming=mg;Endprocess;Enda;仿真波形图：--Hour1（时计数器4进制与2进制）Libraryieee;Useieee.std_logic_1164.all;Useieee.std_logic_unsigned.all;Entityhour1isPort(clkh,set:instd_logic;h1,h0:instd_logic_vector(3downto0);hours,hourg:bufferstd_logic_vector(3downto0);enhour:outstd_logic);End;Architectureaofhour1isBeginProcess(clkh,set)variablehs,hg:std_logic_vector(3downto0);variableho:std_logic;BeginIfset='1'thenhs:=h1;hg:=h0;Elsifclkh'eventandclkh='1'thenifhs=0010andhg=0011thenhs:=0000;hg:=0000;ho:='1';elsifhg1001thenhg:=hg+1;ho:='0';elsifhg=1001thenhg:=0000;hs:=hs+1;ho:='0';endif;endif;hours=hs;hourg=hg;enhour=ho;Endprocess;Enda;仿真波形图：Libraryieee;(星期计数器，7进制)Useieee.std_logic_1164.all;Useieee.std_logic_arith.all;Useieee.std_logic_unsigned.all;EntityweekisPort(clkd,set,reset:instd_logic;d1:instd_logic_vector(3downto0);--――置数端（星期）day:bufferstd_logic_vector(3downto0));--――星期输出端end;ArchitectureaofweekisBeginProcess(clkd,reset,set,d1)BeginIfreset='0'thenday=0000;--――对星期计时器清0Elsifset='0'thenday=d1;--――对星期计时器置d1的数Elsifclkd'eventandclkd='1'thenIfday=6thenday=0000;--――重复计数Elseday=day+1;Endif;Endif;Endprocess;End;仿真波形图：--Second2(秒置数模块，6进制和10进制)Libraryieee;Useieee.std_logic_1164.all;Useieee.std_logic_unsigned.all;Entitysecond2isPort(clks1:instd_logic;Secs,Secg:outstd_logic_vector(3downto0));End;Architectureaofsecond2isBeginProcess(clks1)variabless,sg:std_logic_vector(3downto0);--(ss:秒十位；sg秒个位)Beginifclks1'eventandclks1='1'thenifss=0101andsg=1001thenss:=0000;sg:=0000;elsifsg1001thensg:=sg+1;elsifsg=1001thensg:=0000;ss:=ss+1;endif;endif;Secs=ss;Secg=sg;endprocess;Enda;仿真波形图：--Min2（分置数模块，6进制和10进制）Libraryieee;Useieee.std_logic_1164.all;Useieee.std_logic_unsigned.all;Entitymin2isPort(clkm1:instd_logic;mins,ming:bufferstd_logic_vector(3downto0));End;Architectureaofmin2isBeginProcess(clkm1)variablems,mg:std_logic_vector(3downto0);Beginifclkm1'eventandclkm1='1'thenifms=0101andmg=1001thenms:=0000;mg:=0000;elsifmg1001thenmg:=mg+1;elsifmg=1001thenmg:=0000;ms:=ms+1;endif;endif;mins=ms;ming=mg;Endprocess;Enda;仿真波形图：--Hour2（时置数模块，4进制与2进制）Libraryieee;Useieee.std_logic_1164.all;Useieee.std_logic_unsigned.all;Entityhour2isPort(clkh1:instd_logic;hours,hourg:bufferstd_logic_vector(3downto0));End;Architectureaofhour2isBeginProcess(clkh1)variablehs,hg:std_logic_vector(3downto0);Beginifclkh1'eventandclkh1='1'thenifhs=0010andhg=0011thenhs:=0000;hg:=0000;elsifhg1001thenhg:=hg+1;elsifhg=1001thenhg:=0000;hs:=hs+1;endif;endif;hours=hs;hourg=hg;Endprocess;Enda;仿真波形图：Libraryieee;（星期置数模块，7进制）Useieee.std_logic_1164.all;Useieee.std_logic_arith.all;Useieee.std_logic_unsigned.all;Entityweek2isPort(clkd1:instd_logic;day:bufferstd_logic_vector(3downto0));--――星期输出端end;Architectureaofweek2isBeginProcess(clkd1)Beginifclkd1'eventandclkd1='1'thenIfday=6thenday=0000;--――重复计数Elseday=day+1;Endif;Endif;Endprocess;End;仿真波形图：libraryieee;（闹钟设置模块）useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitynzisport(ml,mh:instd_logic_vector(3downto0);hl,hh:instd_logic_vector(3downto0);mlo,mho:instd_logic_vector(3downto0);hlo,hho:instd_logic_vector(3downto0);set:instd_logic;output:outstd_logic);endnz;architecturebehavofnzissignalopt:std_logic;beginprocess(set,ml,mh,hl,hh,mlo,mho,hlo,hho)beginifset='1'thenif(ml=mloandmh=mhoandhl=hloandhh=hho)thenopt='1';elseopt='0';endif;endif;output=opt;endprocess;endbehav;libraryieee;（闹钟响铃时长设置）useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitytimesetisport(nz:instd_logic;sj:inintegerrange0to1200;clk:instd_logic;ring:outstd_logic