课程:CPLD与FPGA设计及应用实验:基于VHDL语言的数字时钟设计学号:092030030姓名:朱峰专业:信号与信息处理学院:电子与信息学院2011年12月基于VHDL语言的数字时钟设计一:主要功能1:具有时、分、秒计数显示功能,以24小时循环计时。2:具有日期和星期显示功能。3:具有秒表功能4:具有调节日期,星期,小时,分钟,清零的功能。5:具有定时和闹铃的功能。二:结构框图三:RTL图clk_insetstopclk_out1clk_out2clkresetenseconddaout[6..0]clkresetsetclksetminenmindaout[6..0]clkresetsetclksethourenhourdaout[6..0]clkresetsetclksetweekenweekdaout[6..0]clkresetweekout[3..0]clkresetmonthout[4..0]dateout[5..0]clk1resetshowweekms[6..0]sec[6..0]min[6..0]hour[6..0]month[4..0]date[5..0]week[3..0]dpled[6..0]sel[7..0]clkspeaksec[6..0]speakmin[6..0]speakdiv:u1msecond:u2second:u3minute:u4hour:u5weeker:u6date:u7seltime:u8speaker:u9clk_inresetsetminsethoursetstopdpspeaksel[7..0]led[6..0]setweekshowweek控制单元使能信号数字时钟CLK时钟信号报警(闹铃)信号复位信号输出信号LED显示扬声器四:功能实现4.1分频模块设计本设计使用的输入时钟信号为50Mhz,经过分频产生两路时钟信号,其中一路为微秒计数时钟信号,一路为动态扫描时钟信号。同时模块有一输入控制信号,其功能是停止微秒计数时钟信号,以实现定时的功能。输入:clk_in为50Mhz,setstop为微秒计数时能信号输出:clk_out1为1/60hzclk_out2为1khz源代码如下:libraryieee;useieee.std_logic_1164.all;entitydivisport(clk_in,setstop:instd_logic;clk_out1,clk_out2:outstd_logic);endentitydiv;architecturefunofdivisconstanta:integer:=8333333;constantb:integer:=49999;signalc:integerrange0toa;signald:integerrange0tob;beginprocess(clk_in,setstop)beginif(clk_in'eventandclk_in='1')thenif((c+7500000)aandsetstop='1')thenc=c+1;clk_out1='1';elsec=0;clk_out1='0';endif;endif;endprocess;process(clk_in)beginif(clk_in'eventandclk_in='1')thenifd=bthend=d+1;clk_out2='1';elsed=0;clk_out2='0';endif;endif;endprocess;endfun;4.2计时模块设计4.2.1微秒计时模块计数器的第一个模块为微秒计时模块,其实质为一个六十进制计数器。输入:clk为1/60hz,reset为清零复位键输出:ensecond为秒模块的进位信号Daout为微妙输出显示信号源代码如下:libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitymsecondisport(clk,reset:instd_logic;ensecond:outstd_logic;daout:outstd_logic_vector(6downto0));endentitymsecond;architecturefunofmsecondissignalcount:std_logic_vector(6downto0);signalenmin_1:std_logic;beginprocess(clk,reset)beginif(reset='0')thencount=0000000;elsif(clk'eventandclk='1')thenif(count(3downto0)=1001)thenif(count16#60#)thenif(count=1011001)thenenmin_1='1';count=0000000;elsecount=count+7;endif;elsecount=0000000;endif;elsif(count16#60#)thencount=count+1;enmin_1='0';elsecount=0000000;endif;endif;endprocess;daout=count;ensecond=enmin_1;endfun;4.2.2秒计时模块计数器的第二个模块为秒计时模块,其实质为一个六十进制计数器。输入:clk为秒进位信号,reset为清零复位键,setmin为调分信号,setclk为消抖时钟输出:enmin为分模块的进位信号daout为秒输出显示信号源代码如下:libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitysecondisport(clk,setclk,reset,setmin:instd_logic;enmin:outstd_logic;daout:outstd_logic_vector(6downto0));endentitysecond;architecturefunofsecondissignalcount:std_logic_vector(6downto0);signalenmin_1,enmin_2:std_logic;beginprocess(clk,reset,setmin)beginif(reset='0')thencount=0000000;elsif(clk'eventandclk='1')thenif(count(3downto0)=1001)thenif(count16#60#)thenif(count=1011001)thenenmin_1='1';count=0000000;elsecount=count+7;endif;elsecount=0000000;endif;elsif(count16#60#)thencount=count+1;enmin_1='0';elsecount=0000000;endif;endif;endprocess;process(setclk,setmin)beginif(setclk'eventandsetclk='1')thenenmin_2=notsetmin;endif;endprocess;daout=count;enmin=(enmin_1orenmin_2);endfun;4.2.3分计时模块计数器的第三个模块为秒计时模块,其实质为一个六十进制计数器。输入:clk为分进位信号,reset为清零复位键,sethour为调时信号,setclk为消抖时钟输出:enhour为小时模块的进位信号daout为分输出显示信号源代码如下:libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityminuteisport(clk,setclk,reset,sethour:instd_logic;enhour:outstd_logic;daout:outstd_logic_vector(6downto0));endentityminute;architecturefunofminuteissignalcount:std_logic_vector(6downto0);signalenhour_1,enhour_2:std_logic;beginprocess(clk,reset)beginif(reset='0')thencount=0000000;elsif(clk'eventandclk='1')thenif(count(3downto0)=1001)thenif(count16#60#)thenif(count=1011001)thenenhour_1='1';count=0000000;elsecount=count+7;endif;elsecount=0000000;endif;elsif(count16#60#)thencount=count+1;enhour_1='0';elsecount=0000000;endif;endif;endprocess;process(setclk,sethour)beginif(setclk'eventandsetclk='1')thenenhour_2=notsethour;endif;endprocess;daout=count;enhour=(enhour_1orenhour_2);endfun;4.2.4小时计时模块计数器的第四个模块为小时计时模块,其实质为一个二十四进制计数器。输入:clk为分进位信号,reset为清零复位键,setweek为调小时信号,setclk为消抖时钟输出:enweek为日期模块的进位信号daout为小时输出显示信号源代码如下:libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityhourisport(clk,setclk,reset,setweek:instd_logic;enweek:outstd_logic;daout:outstd_logic_vector(6downto0));endentityhour;architecturefunofhourissignalcount:std_logic_vector(6downto0);signalenweek_1,enweek_2:std_logic;beginprocess(clk,reset)beginif(reset='0')thencount=0000000;elsif(clk'eventandclk='1')thenif(count(3downto0)=1001)and(count16#23#)thencount=count+7;elsif(count=0100011)thenenweek_1='1';count=0000000;elsif(count16#23#)thencount=count+1;enweek_1='0';elsecount=0000000;endif;endif;endprocess;process(setclk,setweek)beginif(setclk'eventandsetclk='1')thenenweek_2=notsetweek;endif;endprocess;daout=count;enweek=(enweek_1orenweek_2);endfun;4.3日期和星期模块设计4.3.1星期显示模块星期显示模块其实质为一个七进制计数器。输入:clk为日期进位信号,reset为清零复位键输出:weeoutk为星期输出显