VHDL 六十进制计数器

libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitycount60isport(clk,clk0,cin,bcd1wr,bcdswr:instd_logic;datain:instd_logic_vector(3downto0);co:outstd_logic;a,b,c,d,e,f,g:outstd_logic;sel:outstd_logic_vector(2to0));endcount60;architectureartofcount60issignalbcd1n:std_logic_vector(3downto0);signalbcdsn:std_logic_vector(2downto0);signaloutda:std_logic_vector(6downto0);beginprocess(clk,bcd1wr)beginif(bcd1wr='1')thenbcd1n=datain;elsif(clk'eventandclk='1')thenif(cin='1')thenif(bcd1n=9)thenbcd1n=0000;elsebcd1n=bcd1n+1;endif;endif;endif;endprocess;process(clk,bcdswr)beginif(bcdswr='1')thenbcdsn=datain(2downto0);elsif(clk'eventandclk='1')thenif(cin='1'andbcd1n=9)thenif(bcdsn=5)thenbcdsn=000;elsebcdsn=bcdsn+1;endif;endif;endif;endprocess;process(bcd1n,bcdsn,cin)beginif(bcd1n=9andbcdsn=5andcin='1')thenco='1';elseco='0';endif;endprocess;process(clk0,bcd1n,bcdsn)beginifclk0='1'thensel=000;casebcd1niswhen0000=outda=1111110;when0001=outda=0110000;when0010=outda=1101101;when0011=outda=1111001;when0100=outda=0110011;when0101=outda=1011011;when0110=outda=1011111;when0111=outda=1110000;when1000=outda=1111111;when1001=outda=1111011;whenothers=outda=0000000;endcase;elsesel=110;casebcdsniswhen000=outda=1111110;when001=outda=0110000;when010=outda=1101101;when011=outda=1111001;when100=outda=0110011;when101=outda=1011011;whenothers=outda=0000000;endcase;endif;a=outda(6);b=outda(5);c=outda(4);d=outda(3);e=outda(2);f=outda(1);g=outda(0);endprocess;endart;