河南科技大学硕士学位论文基于DSP和FPGA运动控制器的设计与研究姓名:郭丹丹申请学位级别:硕士专业:机械电子工程指导教师:任德志@IDSPFPGAASICPCDSPFPGADSPFPGA123456“NCPC”IISubject:TheDesignandResearchoftheMotionControllerbasedonDSPandFPGASpecialty:MechatronicsEngineeringName:GuoDandanSupervisor:RenDezhiAssociateProfessorABSTRACTMotioncontroltechnologyhasbeendevelopedfromthespecificmotioncontroltechnologyfortraditionalNCmanufacturingtotheadvancedmotioncontroltechnologywhichownsopenstructureandcanbefastreconstructedwithconcreteapplicationdemand.AndmotioncontrollerhasbeendevelopedfromthemotioncontrollerbasedonMCUandmicroprocessororbasedonASICtotheopenmotioncontrollerwithDSPandFPGAbasedonPCbus.Inthispaper,domesticandinternationalnewestachievementinmotioncontroltechnologyisanalyzedandresearchedthoroughly.AndthemotioncontrollerbasedonDSPandFPGAisdesignedandresearched.Themainresearchcontentsareasfollows:Firstly,thedomesticandoverseasactualityandtrendofmotioncontroltechnologyisanalyzedandresearched.Secondly,thedesignprojectofthemotioncontrollerisconfirmed.Thirdly,thestructureandfunctionofthemainmoduleforthemotioncontrollerisdesigned.Fourthly,motioncontrolarithmeticanddigitalservofilterarithmeticisdesigned.Andcontrolsoftwareisprogrammed.Fifthly,theperformanceofthemotioncontrolsystemisanalyzed.Controllerparametersisadjustedthroughsimulatinginordertoenablethesystemtogetpreferablestaticanddynamicperformance.Sixthly,experimentsystemisconstructed.GUIsoftwareisprogrammedtovalidatetheperformanceofthemotioncontroller.Themotioncontrollercanprovideahardwareandsoftwareplatform,onwhichmanymotioncontrolproblemsofelectromechanicalintegrationsystemcanbenumericallysettledAlsoitcanbeusedtoconstructtheopenNCsystemwiththe“NCembeddedinPC”architectureIIIKEYWORDSMotionController,MotionControlTechnology,AcceleratingandDeceleratingControlArithmetic,DigitalServoFilterDissertationType:ApplicationResearch1111.1[1]1-11-1Fig.1-1MotionControlSystemConstructionDiagramPC/21.21987NGC[2-4](OSACA)1996NGCEMCOMACOMACAPTOSEC(OpenSystemEnvironmentforController)[2-4]MazakIBMSMLFAOSECPC+OSEC371-2FADLDeltaTau,Galil,DMC,AerotechTech80PLC(AIME)80%13NC1-2OSECFig.1-2OSECOpenNumericalControlSystem1.319994[5-8]PCDOS1.4CPU41“”23PCDSPFPGA1.51PC2342351.62522.11PCPC2345[9]2.22.2.11986206(PC)2090DSPFPGA(fieldprogrammablegatearray)DSPFPGADSPTexasInstrumentsTMS320C31(AnalogDevices)ADSP-21061SHARC(Motorola)DSP5600FPGAAlteraFlex10K10DSP232PCISA/PCI20µsFPGADSPFPGAPCWindowsNTJAVAIEDSPFPGA[10,11]2.2.2DSPFPGA[12-16]2-11PCPC22-1/D/A.A/D27PC2-1Fig.2-1MotionControlSystemStructureDiagram3456DSPPCPC“PC+”“PC”PC2-28DSPTITMS320LF2407AFPGAAlteraACEX1KEP1K30QC208D/AAD16DAC-10V~+10V(ABZ)TISN75175FPGADSP3FPGAI/ODSPDSPD/A1644ISAIOD/AFPGA(ABZ)4Home8Limit8442DACCAN280316CANPC2-2Fig.2-2SystemHardwareStructure292.32.3.1“”()DSP2.3.2PCDSP2-3PCCIMSCAD/CAMI/ODSPDSPPCPCPCDSP10ISADSPPC2-3Fig.2-3SystemSoftwareStructure2.4DSPFPGA[17]31133.1TITMS320LF2407AFPGAALTERAEP1K30QC2083.1.1DSPTMS320LF2407ADSPFFTDSPALUDSPTMS320C24xDSPTIDSPTMS320LF2407ATMS320C24x[18,19]1CMOS3.3V40MIPS2TMS320C2xxCPUTMS320LF240xADSPTMS320DSP332KFLASH1.5K/RAM544RAMDARAM2KRAMSARAM4EVAEVB16816PWMPWMPDPINTxPWMPWM31216A/D5192K64K64K64KI/O6WDT710A/D375ns8A/D16A/D8CAN2.0B9SCI1016SPI111240/GPIO1351433.1.2FPGAEP1K30QC208FPGAALTERAACEX1KPLDS[20,21]11102-13-1ACEX1KTab.3-1ACEX1KDeviceFeaturesEP1K10EP1K30EP1K50EP1K10010,00030,00050,000100,00056,000119,000199,000257,000(LE)5761,7282,8804,992EAB361012RAMbit12,28824,57640,96049,152I/O1361712493332I/O2.5V3.3V5VI/O313250MHzPCIPCI2.233MHz66MHz3.3V3-1PCI2.25VJTAGBSTIEEEStd.1149.12.5VJTAGICR100%I/O4645I/OI/OVCCIO3.2DSPDSPPC3.2.1DSPDSPI/ODSPI/OI/O141A158000HA1A0ISA2A144000HA2~A0D/A3A121000HA3~A0I/O4A11800HA3~A05A10400HA3~A06A780HA3~A03.2.2DSPPCDSPPCISADSPISAFPGA3-1[22]CPISNCPR_WNCPSTRBNCPA15CPA1CPA0CPINTNHW_RSNCPD[15..0]RESETIOCS16NIOWNIORNAENSA[11..1]SW[4..1]BD[15..0]FPGA3-1DSPPCFig.3-1DSP-PCInterfaceModule3-1SW[4..1]ISADSP1RESETISA2IOCS16NPC816163IOWNPC3154IORNPC5AEN6SA[11..1]7BD[15..0]8SW[4..1]FPGA74688SW[4..1]SA[11..8]=3HSW[4..1]0SA[7..4]=0300HPCPCPCPCDSPPCDSP2DSPPCPC1332211DSP161PC2DSP300HPC300HPC300HPC302HPC1302HPCPC308HHW_RSNHW_RSNRESETPCHW_RSN3.2.3-10V~+10VLF2407D/AD/AAD16DAC16AD18663-2[23-25]10K100K123114V-V+OP497A10K100K-12V+12VVOUT1567OP497B10K10K100K100KVOUT2AD1866VCCLLDLCLKLRDRDGNDVCCVBLVOLNRLAGNDVBRVORNRRVCC123456789101112131415165V5VAGND5VDGNDDA_CKLDAC1LDAC2SDATASDATA3-2Fig.3-2AnalogVoltageOutputCircuit3-2DA_CKSDATALDAC1LDAC2LDAC3LDAC4SDATADA_CKAD1866D/AD/AAD1866VOLVORVBLVBR2.5VAD1866±1VVOLVOR+1.5V+3.5VVOLVOROP497DAC1DAC2()1102.5DACVOL=×−()2102.5DACVOR=×−AD186616DSP16AD1866DSP1616FPGA3-33-3DSP3-2DACAD1866317FPGACPISNCPR_WNCPSTRBNCPA14CPA2CPA1CPA010MCLKCPD[15..0]DA_CKLDAC4LDAC3LDAC2LDAC1SDATA3-3Fig.3-3ParallelModetoSerialModeLogicInterfaceModule4000H1DAC4002H2DAC4004H3DAC4006H4DACDSP16163.2.4A/AB/BZ/Z13-4[26]A-A+ENA/CC+C-B-B+ENB/DD-D+VCCOUTAOUTCOUTBOUTDGNDSN75175123456789101112131415165VGNDENCA1ENCB1ENCZ15V5VRRR/CHA1CHA1/CHB1CHB1/CHZ1CHZ13-4Fig.3-4DifferenceFilterCircuit183-4ENCA1ENCB1ENCZ1FPGA[27-30]140MCLK3-53-5Fig.3-5DigitalFilter3-6Fig.3-64-TimesF