3.0 PCIE-PHY Interface for the PCI Express Archite

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2020-03-13

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PHYInterfaceforthePCIExpress*ArchitecturePCIExpress3.0Revision0.5August2008©2007,2008IntelCorporation—Allrightsreserved.PHYInterfaceforthePCIExpress*Architecture©2007,2008IntelCorporation—Allrightsreserved.*Othernamesandbrandsmaybeclaimedasthepropertyofothers.Page2of45IntellectualPropertyDisclaimerTHISSPECIFICATIONISPROVIDED“ASIS”WITHNOWARRANTIESWHATSOEVERINCLUDINGANYWARRANTYOFMERCHANTABILITY,FITNESSFORANYPARTICULARPURPOSE,ORANYWARRANTYOTHERWISEARISINGOUTOFANYPROPOSAL,SPECIFICATION,ORSAMPLE.ACOPYRIGHTLICENSEISHEREBYGRANTEDTOREPRODUCEANDDISTRIBUTETHISSPECIFICATIONFORINTERNALUSEONLY.NOOTHERLICENSE,EXPRESSORIMPLIED,BYESTOPPELOROTHERWISE,TOANYOTHERINTELLECTUALPROPERTYRIGHTSISGRANTEDORINTENDEDHEREBY.INTELCORPORATIONANDTHEAUTHORSOFTHISSPECIFICATIONDISCLAIMALLLIABILITY,INCLUDINGLIABILITYFORINFRINGEMENTOFPROPRIETARYRIGHTS,RELATINGTOIMPLEMENTATIONOFINFORMATIONINTHISDOCUMENTANDTHESPECIFICATION.INTELCORPORATIONANDTHEAUTHORSOFTHISSPECIFICATIONALSODONOTWARRANTORREPRESENTTHATSUCHIMPLEMENTATION(S)WILLNOTINFRINGESUCHRIGHTS.ALLSUGGESTIONSORFEEDBACKRELATEDTOTHISSPECIFICATIONBECOMETHEPROPERTYOFINTELCORPORATIONUPONSUBMISSION.INTELCORPORATIONMAYMAKECHANGESTOSPECIFICATIONS,PRODUCTDESCRIPTIONS,ANDPLANSATANYTIME,WITHOUTNOTICE.Notice:Implementationsdevelopedusingtheinformationprovidedinthisspecificationmayinfringethepatentrightsofvariouspartiesincludingthepartiesinvolvedinthedevelopmentofthisspecification.Nolicense,expressorimplied,byestoppelorotherwise,toanyintellectualpropertyrights(includingwithoutlimitationrightsunderanyparty’spatents)aregrantedherein.Thisdocumentisanintermediatedraftforcommentonlyandissubjecttochangewithoutnotice.Readersshouldnotdesignproductsbasedonthisdocument.Allproductnamesaretrademarks,registeredtrademarks,orservicemarksoftheirrespectiveownersPHYInterfaceforthePCIExpress*Architecture©2007,2008IntelCorporation—Allrightsreserved.*Othernamesandbrandsmaybeclaimedasthepropertyofothers.Page3of45TableofContents1Preface......................................................................................................................................71.1ScopeofthisRevision......................................................................................................71.2RevisionHistory...............................................................................................................72Introduction..............................................................................................................................82.1PCIExpressPHYLayer...................................................................................................93PHY/MACInterface..............................................................................................................104PCIExpressPHYFunctionality.............................................................................................124.1TransmitterBlockDiagram(2.5and5.0GT/s)..............................................................134.2TransmitterBlockDiagram(8.0GT/s)...........................................................................144.3ReceiverBlockDiagram(2.5and5.0GT/s)..................................................................154.4ReceiverBlockDiagram(8.0GT/s)...............................................................................164.5Clocking..........................................................................................................................175PIPEInterfaceSignalDescriptions........................................................................................175.1PHY/MACInterfaceSignals..........................................................................................175.2ExternalSignals..............................................................................................................256PIPEOperationalBehavior....................................................................................................266.1Clocking..........................................................................................................................266.2Reset................................................................................................................................266.3PowerManagement........................................................................................................276.4ChangingSignalingRate................................................................................................286.4.1Fixeddatapathimplementations.............................................................................296.4.2FixedPCLKimplementations.................................................................................296.5TransmitterMargining....................................................................................................306.6SelectableDe-emphasis..................................................................................................316.7ReceiverDetection........................................................................