vhdl试题选

写出模为24（0~23）的8421BCD码加法计数器的VHDL描述。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYtbISPORT(clk:INSTD_LOGIC;shi,ge:OUTINTEGERRANGE0TO9);END;ARCHITECTUREbhvOFtbISSIGNALshi1,ge1:INTEGERRANGE0TO9;BEGINPROCESS(clk)BEGINIFclk'EVENTANDclk='1'THENIFge1=9THENge1=0;shi1=shi1+1;ELSIFshi1=2ANDge1=3THENshi1=0;ge1=0;ELSEge1=ge1+1;ENDIF;ENDIF;ENDPROCESS;ge=ge1;shi=shi1;ENDbhv;LIBRARYIEEE；USEIEEE.STD_LOGIC_1164.ALL；ENTITYinstruction_decoderISPORT（code：INStd_logic_Vector(2DOWNTO0)；data_l，data_r：INStd_Logic；result：OUTStd_Logic)；ENDinstruction_decoder；ARCHITECTUREbehavlOFinstruction_decoderISBEGINPROCESS(code，data_l，data_r)BEGINCASEcodeISWHEN″000″=result=data_lANDdata_r；WHEN″001″=result=data_lNANDdata_r；WHEN″010″=result=data_lORdata_r；WHEN″011″=result=data_lNORdata_r；WHEN″100″=result=data_lXORdata_r；WHEN″101″=result=data_lXNORdata_r；WHENOTHERS=result=′Z′；ENDCASE；ENDPROCESS；ENDbehavl；画出下面VHDL描述的指令译码器的内部逻辑电路图3codedata_ldata_r000101100011010001result111110+Vdd000101100011010001111110x:=in3&in2&in1&in0；CASExISWHEN″0001″=y=″00″；WHEN″0010″=y=″01″；WHEN″0100″=y=″10″；WHEN″1000″=y=″11″；WHENOTHERS=y=″--″；ENDCASE；END；END；①缺少Std_logic类型的声明。在实体声明之前添加LIBRARYIEEE；USEIEEE.Std_logic_1164.ALL；②敏感信号表不完整。应为PROCESS（in0，in1，in2，in3）。③变量x的下标位数不正确。下标应当为“3DOWNTO0”。④变量声明应当在进程语句之中。将变量声明“VARIABLEx：Std_logic_vector(3DOWNTO0)；”置于“PROCESS（in0，in1，in2，in3）”之后。⑤进程的结束语句不正确。应将倒数第2句“END；”改为“ENDPROCESS；”。指出下列VHDL描述中的多处．．错误，并修改之：（10分）ENTITYencoderISPORT（in0，in1，in2，in3：INStd_logic；y：OUTStd_logic_vector(1DOWNTO0)）；ENDencoder；ARCHITECTUREbehvlOFencoderISVARIABLEx：Std_logic_vector(2DOWNTO0)；BEGINPROCESS（in0，in1，in3）BEGIN用VHDL描述一个四相四拍顺序脉冲发生器。当dir=′0′时，在clk的上升沿按照a、b、c、d的顺序发生单相脉冲；当dir=′1′时，在clk的上升沿按照d、c、b、a的顺序发生单相脉冲LIBRARYIEEE；USEIEEE.Std_logic_1164.ALL；ENTITYsequencerISPORT(clk，dir，ind：INStd_logic；a，b，c，d：OUTStd_logic)；ENDsequencer；ARCHITECTUREbehavl_seqOFsequencerISSIGNALx：Std_logic_vector(3DOWNTO0)；BEGINPROCESS（clk,ind）BEGINIFind='1'THENx=(OTHERS='0');IF（clk′EventANDclk=′1′)THENCASExISWHEN″0001″=IFdir=′0′THENx=″0010″；ELSEx=″1000″；ENDIF；WHEN″0010″=IFdir=′0′THENx=″0100″；ELSEx=″0001″；ENDIF；WHEN″0100″=IFdir=′0′THENx=″1000″；ELSEx=″0010″；ENDIF；WHEN″1000″=IFdir=′0′THENx=″0001″；ELSEx=″0100″；ENDIF；WHENOTHERS=x=″0001″；ENDCASE；ENDIF；ENDPROCESS；a=x(0)；b=x(1)；c=x(2)；d=x(3)；ENDbehavl_seq；dirabcdclk四相四拍顺序脉冲发生器ARCHITECTUREbehavl_2OFsequencerISSIGNALx:Std_logic_vector(3DOWNTO0);BEGINPROCESS(clk)BEGINIFclk'EventANDclk='1'THENCASExISWHEN0001=x=0010;WHEN0010=x=0100;WHEN0100=x=1000;WHEN1000=x=0001;WHENOTHERS=x=0001;ENDCASE;ENDIF;ENDPROCESS;PROCESS(dir)BEGINIFdir='0'THENa=x(0);b=x(1);c=x(2);d=x(3);ELSEa=x(3);b=x(2);c=x(1);d=x(0);ENDIF;ENDPROCESS;ENDbehavl_2;ARCHITECTUREbehavl_3OFsequencerISSIGNALx:Std_logic_vector(3DOWNTO0);BEGINPROCESS(clk,dir)BEGINIFdir='0'THENx='0001;IFclk'EventANDclk='1'THENCASExISWHEN0001=x=0010;WHEN0010=x=0100;WHEN0100=x=1000;WHEN1000=x=0001;WHENOTHERS=x=0001;ENDCASE;ENDIF;ELSEx=0001;IFclk'EventANDclk='1'THENCASExISWHEN0001=x=1000;WHEN0010=x=0001;WHEN0100=x=0010;WHEN1000=x=0100;WHENOTHERS=x=0001;ENDCASE;ENDIF;ENDIF;ENDPROCESS;a=x(0);b=x(1);c=x(2);d=x(3);ENDbehavl_3;一、下图所示是一个2FSK调制电路的逻辑框图，试用VHDL描述它的实体声明和顶层结构体声明：（10分）LIBRARYIEEE；USEIEEE.STD_LOGIC_1164.ALL；ENTITYBFSKISPORT（clock，code_in：INStd_logic；fsk2：OUTStd_Logic)；ENDBFSK；ARCHITECTUREtopOFBFSKISSIGNALf1，f2：Std_logic；COMPONENTDividerPORT（clk：INStd_logic；q：OUTStd_logic）；ENDCOMPONENT；BEGINU0：DividerPORTMAP（clk=clock，q=f1）；U1：DividerPORTMAP（clk=clock，q=f2）；PROCESS(code_in，f1，f2)BEGINIFcode_in='0'THENfsk2=f1；ELSEfsk2=f2；ENDIF；ENDPROCESS；END；时钟源clock数字基带信号code_inDivider1Divider22FSK信号fsk2载波f1载波f2ENDCOMPONENT；COMPONENTcounterPORT（clk：INStd_logic；Dvalid，Hsync，Vsync：OUTStd_logic；Data：OUTStd_logic_Vector(15DOWNTO0))；ENDCOMPONENT；BEGINU0：freq_divPORTMAP（clk=clock，q=pclk）；U1：counterPORTMAP（clk=pclk，Dvalid=Dvalid，Hsync=Hsync，Vsync=Vsync，Data=Data）；END；二、下图所示是一个信号发生器的逻辑框图，试用VHDL描述它的实体声明和顶层结构体声明：（10分）LIBRARYIEEE；USEIEEE.STD_LOGIC_1164.ALL；ENTITYgeneratorISPORT(clock：INStd_logic；Dvalid，Hsync，Vsync：OUTStd_logic；Data：OUTStd_logic_Vector(15DOWNTO0))；ENDgenerator；ARCHITECTUREtopOFgeneratorISSIGNALpclk：Std_logic；COMPONENTfreq_divPORT（clk：INStd_logic；q：OUTStd_logic）；16freq_divcounterclockpclkgenerator信号发生器DvalidDataHsyncVsync三、指出下列VHDL描述中的多处．．错误，并修改之：（10分）LIBRARYIEEE；ENTITYadderISPORT(a，b：INSTD_LOGIC_VECTOR(3DOWNTO0)；carry_in：INSTD_LOGIC；sum_out：OUTSTD_LOGIC_VECTOR(3DOWNTO0)；carry_out：OUTSTD_LOGIC)；END；ARCHITECTUREbehaveOFadderISBEGINPROCESS(a，b)SIGNALsum：STD_LOGIC_VECTOR(3DOWNTO0)；SIGNALcarry：STD_LOGIC；BEGINcarry:='0'；FORiIN0TO3LOOPsum(i):=a(i)XORb(i)XORcarry；carry:=(a(i)ANDb(i))OR(a(i)ANDcarry)OR(b(i)ANDcarry)；ENDLOOP；sum_out=sum；carry_out=carry；END；END；LIBRARYIEEE；USEIEEE.STD_LOGIC_1164.ALL；①缺少USE子句ENTITYadderISPORT(a，b：INSTD_LOGIC_VECTOR(3DOWNTO0)；carry_in：INSTD_LOGIC；sum_out：OUTSTD_LOGIC_VECTOR(3DOWNTO0)；carry_out：OUTSTD_LOGIC)；END；ARCHITECTUREbehaveOFadderISBEGINPROCESS(a，b，carry_in)②敏感信号表缺少carry_inVARIABLEsum：STD_LOGIC_VECTOR