TMS320F28035寄存器速查手册

FlashandOTPMemory(1)(2)AddressSize(x16)DescriptionBitDescriptionFOPT0x0A801FlashOptionRegisterFigure4Reserved0x0A811ReservedFPWR0x0A821FlashPowerModesRegisterFigure5FSTATUS0x0A831StatusRegisterFigure6FSTDBYWAIT(3)0x0A841FlashSleepToStandbyWaitRegisterFigure7FACTIVEWAIT(3)0x0A851FlashStandbyToActiveWaitRegisterFigure8FBANKWAIT0x0A861FlashReadAccessWaitStateRegisterFigure9FOTPWAIT0x0A871OTPReadAccessWaitStateRegisterFigure10(1)TheseregistersareEALLOWprotected.SeeSection5.2forinformation.(2)TheseregistersareprotectedbytheCodeSecurityModule(CSM).SeeSection2formoreinformation.(3)Theseregistersshouldbeleftintheirdefaultstate.NOTE:TheflashconfigurationregistersshouldnotbewrittentobycodethatisrunningfromOTPorflashmemoryorwhileanaccesstoflashorOTPmaybeinprogress.Allregisteraccessestotheflashregistersshouldbemadefromcodeexecutingoutsideofflash/OTPmemoryandanaccessshouldnotbeattempteduntilallactivityontheflash/OTPhascompleted.Nohardwareisincludedtoprotectagainstthis.Tosummarize,youcanreadtheflashregistersfromcodeexecutinginflash/OTP;however,donotwritetotheregisters.CPUwriteaccesstotheflashconfigurationregisterscanbeenabledonlybyexecutingtheEALLOWinstruction.WriteaccessisdisabledwhentheEDISinstructionisexecuted.Thisprotectstheregistersfromspuriousaccesses.Readaccessisalwaysavailable.TheregisterscanbeaccessedthroughtheJTAGportwithouttheneedtoexecuteEALLOW.SeeSection5.2forinformationonEALLOWprotection.Theseregisterssupportboth16-bitand32-bitaccesses.16SystemControlSPRUGL8C–May2009–RevisedFebruary2013SubmitDocumentationFeedbackCopyright©2009–2013,TexasInstrumentsIncorporated(FOPT)1510ReservedENPIPER-0R/W-0LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterresetTable2.FlashOptionsRegister(FOPT)FieldDescriptionsBitFieldValueDescription(1)(2)(3)15-1ReservedAnywritestothesebit(s)mustalwayshaveavalueof0.0ENPIPEEnableFlashPipelineModeBit.Flashpipelinemodeisactivewhenthisbitisset.Thepipelinemodeimprovesperformanceofinstructionfetchesbyprefetchinginstructions.SeeSection1.3.2formoreinformation.Whenpipelinemodeisenabled,theflashwaitstates(pagedandrandom)mustbegreaterthanzero.Onflashdevices,ENPIPEaffectsfetchesfromflashandOTP.0FlashPipelinemodeisnotactive.(default)1FlashPipelinemodeisactive.(1)ThisregisterisEALLOWprotected.SeeSection5.2formoreinformation.(2)ThisregisterisprotectedbytheCodeSecurityModule(CSM).SeeSection2formoreinformation.(3)Whenwritingtothisregister,followtheproceduredescribedinSection1.3.4.Figure5.FlashPowerRegister(FPWR)15210ReservedPWRR-0R/W-0LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterresetTable3.FlashPowerRegister(FPWR)FieldDescriptionsBitFieldValueDescription(1)(2)15-2ReservedAnywritestothesebit(s)mustalwayshaveavalueof0.1-0PWRFlashPowerModeBits.Writingtothesebitschangesthecurrentpowermodeoftheflashbankandpump.SeesectionSection1.3formoreinformationonchangingtheflashbankpowermode.00Pumpandbanksleep(lowestpower)01Pumpandbankstandby10Reserved(noeffect)11Pumpandbankactive(highestpower)(1)ThisregisterisEALLOWprotected.SeeSection5.2formoreinformation.(2)ThisregisterisprotectedbytheCodeSecurityModule(CSM).SeeSection2formoreinformation.17SPRUGL8C–May2009–RevisedFebruary2013SystemControlSubmitDocumentationFeedbackCopyright©2009–2013,TexasInstrumentsIncorporatedFlashandOTPMemory(FSTATUS)1598Reserved3VSTATR-0R/W1C-0743210ReservedACTIVEWAITSSTDBYWAITSPWRSR-0R-0R-0R-0LEGEND:R/W=Read/Write;R=Readonly;W1C=Write1toclear;-n=valueafterresetTable4.FlashStatusRegister(FSTATUS)FieldDescriptionsBitFieldValueDescription(1)(2)15-9ReservedAnywritestothesebit(s)mustalwayshaveavalueof0.83VSTATFlashVoltage(VDD3VFL)StatusLatchBit.Whenset,thisbitindicatesthatthe3VSTATsignalfromthepumpmodulewenttoahighlevel.Thissignalindicatesthattheflash3.3-Vsupplywentoutoftheallowablerange.0Writesof0areignored.1Whenthisbitreads1,itindicatesthattheflash3.3-Vsupplywentoutoftheallowablerange.Clearthisbitbywritinga1.7-4ReservedAnywritestothesebit(s)mustalwayshaveavalueof0.3ACTIVEWAITSBankandPumpStandbyToActiveWaitCounterStatusBit.Thisbitindicateswhethertherespectivewaitcounteristimingoutanaccess.0Thecounterisnotcounting.1Thecounteriscounting.2STDBYWAITSBankandPumpSleepToStandbyWaitCounterStatusBit.Thisbitindicateswhethertherespectivewaitcounteristimingoutanaccess.0Thecounterisnotcounting.1Thecounteriscounting.1-0PWRSPowerModesStatusBits.Thesebitsindicatewhichpowermodetheflash/OTPiscurrentlyin.ThePWRSbitsaresettothenewpowermodeonlyaftertheappropriatetimingdelayshaveexpired.00Pumpandbankinsleepmode(lowestpower)01Pumpandbankinstandbymode10Reserved11Pumpandbankactiveandinreadmode(highestpower)(1)ThisregisterisEALLOWprotected.SeeSection5.2formoreinformation.(2)ThisregisterisprotectedbytheCodeSecurityModule(CSM).SeeSection2formoreinformation.18SystemC