嵌入式开发-LPC1759_58_56_54_52_51Cortex-M3内核微控制器数据手册

DRAFTDRAFTDRAFTDRDRAFTDRAFTDRAFTDRAFDRAFTDRAFTDRAFTDRAFTDRAFTDDRAFTDRAFTDRAFTDRAFTDRAFTDRAFTDRA1.GeneraldescriptionTheLPC1759/58/56/54/52/51areARMCortex-M3basedmicrocontrollersforembeddedapplicationsfeaturingahighlevelofintegrationandlowpowerconsumption.TheARMCortex-M3isanextgenerationcorethatofferssystemenhancementssuchasenhanceddebugfeaturesandahigherlevelofsupportblockintegration.TheLPC1758/56/57/54/52/51operateatCPUfrequenciesofupto100MHz.TheLPC1759operatesatCPUfrequenciesofupto120MHz.TheARMCortex-M3CPUincorporatesa3-stagepipelineandusesaHarvardarchitecturewithseparatelocalinstructionanddatabusesaswellasathirdbusforperipherals.TheARMCortex-M3CPUalsoincludesaninternalprefetchunitthatsupportsspeculativebranching.TheperipheralcomplementoftheLPC1759/58/56/54/52/51includesupto512kBofflashmemory,upto64kBofdatamemory,EthernetMAC,USBDevice/Host/OTGinterface,8-channelgeneralpurposeDMAcontroller,4UARTs,2CANchannels,2SSPcontrollers,SPIinterface,2I2C-businterfaces,2-inputplus2-outputI2S-businterface,6channel12-bitADC,10-bitDAC,motorcontrolPWM,QuadratureEncoderinterface,4generalpurposetimers,6-outputgeneralpurposePWM,ultra-lowpowerReal-TimeClock(RTC)withseparatebatterysupply,andupto52generalpurposeI/Opins.2.Features„ARMCortex-M3processor,runningatfrequenciesofupto100MHz(LPC1758/56/57/54/52/51)orofupto120MHz(LPC1759).AMemoryProtectionUnit(MPU)supportingeightregionsisincluded.„ARMCortex-M3built-inNestedVectoredInterruptController(NVIC).„Upto512kBon-chipflashprogrammingmemory.Enhancedflashmemoryacceleratorenableshigh-speed120MHzoperationwithzerowaitstates.„In-SystemProgramming(ISP)andIn-ApplicationProgramming(IAP)viaon-chipbootloadersoftware.„On-chipSRAMincludes:‹Upto32kBofSRAMontheCPUwithlocalcode/databusforhigh-performanceCPUaccess.‹Two/one16kBSRAMblockswithseparateaccesspathsforhigherthroughput.TheseSRAMblocksmaybeusedforEthernet(LPC1759/58only),USB,andDMAmemory,aswellasforgeneralpurposeCPUinstructionanddatastorage.„EightchannelGeneralPurposeDMAcontroller(GPDMA)ontheAHBmultilayermatrixthatcanbeusedwiththeSSP,I2S-bus,UART,theAnalog-to-DigitalandDigital-to-Analogconverterperipherals,timermatchsignals,andformemory-to-memorytransfers.LPC1759/58/56/54/52/5132-bitARMCortex-M3MCU;upto512kBflashand64kBSRAMwithEthernet,USB2.0Host/Device/OTG,CANRev.03.01—16December2009ProductdatasheetDRAFTDRAFTDRAFTDRDRAFTDRAFTDRAFTDRAFDRAFTDRAFTDRAFTDRAFTDRAFTDDRAFTDRAFTDRAFTDRAFTDRAFTDRAFTDRALPC1759_58_56_54_52_51_3©NXPB.V.2009.Allrightsreserved.ProductdatasheetRev.03.01—16December20092of64NXPSemiconductorsLPC1759/58/56/54/52/5132-bitARMCortex-M3microcontroller„MultilayerAHBmatrixinterconnectprovidesaseparatebusforeachAHBmaster.AHBmastersincludetheCPU,GeneralPurposeDMAcontroller,EthernetMAC(LPC1758only),andtheUSBinterface.Thisinterconnectprovidescommunicationwithnoarbitrationdelays.„SplitAPBbusallowshighthroughputwithfewstallsbetweentheCPUandDMA.„Serialinterfaces:‹OntheLPC1759/58only,EthernetMACwithRMIIinterfaceanddedicatedDMAcontroller.‹USB2.0full-speeddevice/Host/OTGcontrollerwithdedicatedDMAcontrollerandon-chipPHYfordevice,Host,andOTGfunctions.TheLPC1752/51includeaUSBdevicecontrolleronly.‹FourUARTswithfractionalbaudrategeneration,internalFIFO,andDMAsupport.OneUARThasmodemcontrolI/OandRS-485/EIA-485support,andoneUARThasIrDAsupport.‹CAN2.0Bcontrollerwithtwo(LPC1759/58/56)orone(LPC1754/52/51)channels.‹SPIcontrollerwithsynchronous,serial,fullduplexcommunicationandprogrammabledatalength.‹TwoSSPcontrollerswithFIFOandmulti-protocolcapabilities.TheSSPinterfacescanbeusedwiththeGPDMAcontroller.‹TwoI2C-businterfacessupportingfastmodewithadatarateof400kbit/swithmultipleaddressrecognitionandmonitormode.‹OntheLPC1759/58/56only,I2S(Inter-ICSound)interfacefordigitalaudioinputoroutput,withfractionalratecontrol.TheI2S-businterfacecanbeusedwiththeGPDMA.TheI2S-businterfacesupports3-wireand4-wiredatatransmitandreceiveaswellasmasterclockinput/output.„Otherperipherals:‹52GeneralPurposeI/O(GPIO)pinswithconfigurablepull-up/downresistors.AllGPIOssupportanew,configurableopen-drainoperatingmode.TheGPIOblockisaccessedthroughtheAHBmultilayerbusforfastaccessandlocatedinmemorysuchthatitsupportsCortex-M3bitbandingandusebytheGeneralPurposeDMAController.‹12-bitAnalog-to-DigitalConverter(ADC)withinputmultiplexingamongsixpins,conversionratesupto200kHz,andmultipleresultregisters.The12-bitADCcanbeusedwiththeGPDMAcontroller.‹OntheLPC1759/58/56/54only,10-bitDigital-to-AnalogConverter(DAC)withdedicatedconversiontimerandDMAsupport.‹Fourgeneralpurposetimers/counters,withatotalofthreecaptureinputsandtencompareoutputs.Eachtimerblockhasanexternalcountinput.SpecifictimereventscanbeselectedtogenerateDMArequests.‹OnemotorcontrolPWMwithsupportforthree-phasemotorcontrol.‹Quadratureencoderinterfacethatcanmonitoroneexternalquadratureencoder.‹OnestandardPWM/timerblockwithexternalcountinput.‹Real-TimeClock(RTC)withaseparatepowerdomainanddedicatedRTCoscillator.TheRTCblockincludes20bytesofbattery-poweredbackupregisters.‹WatchdogTimer(WDT).TheWDTcanbeclockedfromtheinternalRCoscillator,theRTCosci