verilog设计一个串行数据检测器

题目：设计一个串行数据检测器。要求是：连续4个或4个以上为1时输出为1，其他输入情况下为0。代码如下：modulefour_one(x,z,clk,rst,state);inputx,clk,rst;outputz;output[2:0]state;reg[2:0]state;wirez;parameterIDLE='d0,A='d1,B='d2,C='d3,D='d4;assignz=(state==D)?1:0;always@(posedgeclkornegedgerst)if(!rst)beginstate=IDLE;endelsecasex(state)IDLE:if(x==1)beginstate=A;endelsebeginstate=IDLE;endA:if(x==1)beginstate=B;endelsebeginstate=IDLE;endB:if(x==1)beginstate=C;endelsebeginstate=IDLE;endC:if(x==1)beginstate=D;endelsebeginstate=IDLE;endD:if(x==1)beginstate=D;endelsebeginstate=IDLE;enddefault:state=IDLE;endcaseendmodule测试代码如下：`timescale1ns/1psmodulefour_one_tst;regx;regclk,rst;wirez;wire[2:0]state;always#20clk=~clk;always@(posedgeclk)begin#20x={$random}%2;endfour_oneuut(.x(x),.z(z),.clk(clk),.rst(rst),.state(state));initialbeginx=0;clk=0;rst=1;#2rst=0;#50rst=1;#500$stop;endendmodule使用ModelSim仿真波形：