MT48LC16M16A2P

PRODUCTSANDSPECIFICATIONSDISCUSSEDHEREINARESUBJECTTOCHANGEBYMICRONWITHOUTNOTICE.1256Mb:x4,x8,x16SDRAMMicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.256MSDRAM_E.p65–Rev.E;Pub.3/02©2002,MicronTechnology,Inc.256Mb:x4,x8,x16SDRAMKEYTIMINGPARAMETERSSPEEDCLOCKACCESSTIMESETUPHOLDGRADEFREQUENCYCL=2*CL=3*TIMETIME-7E143MHz–5.4ns1.5ns0.8ns-75133MHz–5.4ns1.5ns0.8ns-7E133MHz5.4ns–1.5ns0.8ns-75100MHz6ns–1.5ns0.8ns64Megx432Megx816Megx16Configuration16Megx4x4banks8Megx8x4banks4Megx16x4banksRefreshCount8K8K8KRowAddressing8K(A0–A12)8K(A0–A12)8K(A0–A12)BankAddressing4(BA0,BA1)4(BA0,BA1)4(BA0,BA1)ColumnAddressing2K(A0–A9,A11)1K(A0–A9)512(A0–A8)SYNCHRONOUSDRAMMT48LC64M4A2–16Megx4x4banksMT48LC32M8A2–8Megx8x4banksMT48LC16M16A2–4Megx16x4banksForthelatestdatasheet,pleaserefertotheMicronWebsite:(TopView)54-PinTSOPFEATURES•PC66-,PC100-,andPC133-compliantFullysynchronous;allsignalsregisteredonpositiveedgeofsystemclockInternalpipelinedoperation;columnaddresscanbechangedeveryclockcycleInternalbanksforhidingrowaccess/prechargeProgrammableburstlengths:1,2,4,8,orfullpageAutoPrecharge,includesCONCURRENTAUTOPRECHARGE,andAutoRefreshModesSelfRefreshMode64ms,8,192-cyclerefreshLVTTL-compatibleinputsandoutputsSingle+3.3V±0.3VpowersupplyOPTIONSMARKINGConfigurations64Megx4(16Megx4x4banks)64M432Megx8(8Megx8x4banks)32M816Megx16(4Megx16x4banks)16M16WRITERecovery(tWR)tWR=“2CLK”1A2Package/Pinout54-pinTSOPIIOCPL2(400mil)TG60-ballFBGA(8mmx16mm)(x4,x8)FB4,554-ballFBGA(8mmx14mm)(x16only)FG3Timing(CycleTime)7.5ns@CL=2(PC133)-7E7.5ns@CL=3(PC133)-75SelfRefreshStandardNoneLowpowerL3OperatingTemperatureCommercial(0oCto+70oC)NoneIndustrial(-40oCto+85oC)IT3NOTE:1.RefertoMicronTechnicalNoteTN-48-05.2.Off-centerpartingline.3.ConsultMicronforavailability.4.Notavailableinx16configuration.5.ActualFBGApartmarkingshownonpage58.PartNumberExample:MT48LC16M16A2TG-75Note:The#symbolindicatessignalisactiveLOW.Adash(–)indicatesx8andx4pinfunctionissameasx16pinfunction.VDDDQ0VDDQDQ1DQ2VssQDQ3DQ4VDDQDQ5DQ6VssQDQ7VDDDQMLWE#CAS#RAS#CS#BA0BA1A10A0A1A2A3VDD123456789101112131415161718192021222324252627545352515049484746454443424140393837363534333231302928VssDQ15VssQDQ14DQ13VDDQDQ12DQ11VssQDQ10DQ9VDDQDQ8VssNCDQMHCLKCKEA12A11A9A8A7A6A5A4Vssx8x16x16x8x4x4-DQ0-NCDQ1-NCDQ2-NCDQ3-NC-NC-------------NC-NCDQ0-NCNC-NCDQ1-NC-NC-------------DQ7-NCDQ6-NCDQ5-NCDQ4-NC--DQM------------NC-NCDQ3-NCNC-NCDQ2-NC--DQM-----------*CL=CAS(READ)latency2256Mb:x4,x8,x16SDRAMMicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.256MSDRAM_E.p65–Rev.E;Pub.3/02©2002,MicronTechnology,Inc.256Mb:x4,x8,x16SDRAM60-BALLFBGAASSIGNMENT(TopView)64Megx4SDRAM8mmx16mm“FB”32Megx8SDRAM8mmx16mm“FB”NOTE:FBGApinSymbol,Type,andDescriptionsareidenticaltothelistingofthe54-pinTSOPtableonpage9.ABCDEFGHJKLMNPR12345678DepopulatedBallsNCVssNCVssQVDDQDQ3NCNCNCVssQVDDQDQ2NCNCNCVssNCDQMNCCKA12CKEA11A9A8A7A6A5A4VssVDDNCVDDQNCDQ0VssQNCNCVDDQNCDQ1VssQNCNCVDDNCWE#CAS#RAS#NCNCCS#BA1BA0A0A10A2A1VDDA3ABCDEFGHJKLMNPR12345678DepopulatedBallsDQ7VssNCVssQVDDQDQ6DQ5NCNCVssQVDDQDQ4NCNCNCVssNCDQMNCCKA12CKEA11A9A8A7A6A5A4VssVDDDQ0VDDQNCDQ1VssQNCDQ2VDDQNCDQ3VssQNCNCVDDNCWE#CAS#RAS#NCNCCS#BA1BA0A0A10A2A1VDDA33256Mb:x4,x8,x16SDRAMMicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.256MSDRAM_E.p65–Rev.E;Pub.3/02©2002,MicronTechnology,Inc.256Mb:x4,x8,x16SDRAM54-BALLFBGAASSIGNMENT(TopView)16Megx16SDRAM8mmx14mm“FG”ABCDEFGHJ123456789DepopulatedBallsVssDQ15DQ14DQ13DQ12DQ11DQ10DQ9DQ8NC/SVUDQMCLKA12A11A8A7VssA5VSSQVDDQVSSQVDDQVssCKEA9A6A4VDDQVssQVDDQVSSQVDDCAS#BA0A0A3DQ0VDDDQ2DQ1DQ4DQ3DQ6DQ5LDQMDQ7RAS#WE#BA1CS#A1A10A2VDD4256Mb:x4,x8,x16SDRAMMicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.256MSDRAM_E.p65–Rev.E;Pub.3/02©2002,MicronTechnology,Inc.256Mb:x4,x8,x16SDRAMGENERALDESCRIPTIONThe256MbSDRAMisahigh-speedCMOS,dynamicrandom-accessmemorycontaining268,435,456bits.Itisinternallyconfiguredasaquad-bankDRAMwithasynchronousinterface(allsignalsareregisteredonthepositiveedgeoftheclocksignal,CLK).Eachofthex4’s67,108,864-bitbanksisorga-nizedas8,192rowsby2,048columnsby4bits.Eachofthex8’s67,108,864-bitbanksisorga-nizedas8,192rowsby1,024columnsby8bits.Eachofthex16’s67,108,864-bitbanksisorganizedas8,192rowsby512columnsby16bits.ReadandwriteaccessestotheSDRAMareburstoriented;accessesstartataselectedlocationandcon-tinueforaprogrammednumberoflocationsinapro-grammedsequence.Accessesbeginwiththeregistra-tionofanACTIVEcommand,whichisthenfollowedbyaREADorWRITEcommand.Theaddressbitsregis-teredcoincidentwiththeACTIVEcommandareusedPARTNUMBERARCHITECTUREPACKAGEMT48LC64M4A2TG64Megx454-pinTSOPIIMT48LC64M4A2FB*64Megx460-ballFBGAMT48LC32M8A2TG32Megx854-pinTSOPIIMT48LC32M8A2FB*32Megx860-ballFBGAMT48LC16M16A2TG16Megx1654-pinTSOPIIMT48LC16M16A2FG16Megx1654-ballFBGA*ActualFBGApartmarkingshownonpage58.256MbSDRAMPARTNUMBERStoselectthebankandrowtobeaccessed(BA0,BA1selectthebank;A0–A12selecttherow).Theaddressbitsregisteredcoin