基于FPGA语音识别系统设计与实现

广西师范大学硕士学位论文基于FPGA语音识别系统设计与实现姓名：王明娟申请学位级别：硕士专业：电路与系统指导教师：胡维平20090401IFPGAIIDesignandImplementationofSpeechRecognitionSystemBasedonFPGAAbstractIII11123SOPC2SOPC4SOPCA/D/2sfsfHfLf3400HfHz=60~100LfHz=8sfkHz=∆2xσmax2X2eσ5SOPC2max2()101()6.024.77201()xexXSNRdBgBgσσσ==+−4xσ0.35%max4xXσ=()6.027.2SNRdBB=−1()1HZzµ−=−µ6SOPC1,0(1)()0,nNwnnelse≤≤−⎧=⎨=⎩0.540.46cos[2/(1)],0(1)()0,nNnNwnnelseπ−−≤⎧=⎨=⎩≤−()wn1(1)/20sin(/2)()sin(/2)NjwTjwnTjwTNnNwTHeeewT−−−===∑−01/1/ssffNNT==4/Nπ8/NπsTf∆1sfNT∆=sTf∆7SOPC()xl()nxm()nxm()()()01nxmwmxnmmN=+≤≤−1,0~(1()0,mNwmm=−⎧=⎨=⎩NT012TT()nxmnE120()NnnmExm−==∑nEnM10|()Nnnm|Mxm−==∑nE()nxmnZ[][]101sgn()sgn(1)2NnnnmZxmxm−==−∑−8SOPC[]sgn[]1,(0)sgn1,(0)xxx≥⎧=⎨−⎩nnMZSUV9SOPC()nxm10()()NjwjnnmXexme−−==∑wm)()wnm−()(jwmjwmjwmwnmeeWe∞−−−=−∞−=∑i()()()jwjwjwnjwnXeXeeWe−−⎡⎤=⎣⎦ii2wπ()()1()()2jwjnjjwnXeeWeXeπθθθπdθπ−+−⎡⎤⎡⎤=⎣⎦⎣⎦∫ii()jwWe()jwWe(jwnXe))(jwXe(jwWe))(jwXe()jwnXe()jwXe2/wkNπ=(jwnXe)()2210()()0kkmNjjNNnnnmXeXkxmekNππ−−==∑1)≤≤−()nXk)(jwnX2LnXek()()nXk()nxm10SOPC()()()2*()nnnnSkXkXkXk==i()()*()snenvn=ˆ()sn()snˆ(){ln|[()]|}snIDFTDTFsn=MELMFCC11SOPC()(1)(1)clhlol=−=+()lXk()()()kol=()()1,2,,hlllmlWkXklL==∑()()()()()()()()()()()lkololkclclolWkhlkclkhlhlcl−⎧≤≤⎪−⎪=⎨−⎪≤≤⎪−⎩121Li()log()cos{()}2mfcclcimllNLπ==−∑12SOPC21()()kkikikdnicnii=−=−=+∑∑iDTW13SOPC{(1),(2),(),,()}RRRmRM()Rm{(1),(2),(),,()}TTTnTN()Tn[,]DTR[(),()]dTnRmη11(,iinm)−−(,)iinm111111(1,(,)(1,1)(1,)iiiiiiiinmnmnmnm−−−−−−2)++⎧⎪=++⎨⎪+⎩14SOPCη()11ˆˆ()()[,]min[,]iiiiiiNNiiiinnmnmnDnmDnmηηΦ•===Φ∈=Φ∈=∑∑(1,)aX(1,ab)XX+(1,b)XN+1(2)3aXMN=−2(2)3bXNM=−abXX2322MNNM−≥⎧⎨−≥⎩minmax[,yy]min1,022(2),bbxxXyxMNXx⎧≤≤⎪=⎨⎪N+−⎩≤max2,011(),22aaxxXyxMNXx≤≤⎧⎪=⎨N+−⎪⎩≤(,)(,)min[(1,),(1,1),(1,2)]DxydxyDxyDxyDxy=+−−−−−15SOPCXYMNXaXb(M,N)2**2BBBB=−21210112101()222222NNMNNMDBbbbb−−−−−−+++++++−2(1.00000)2(0.111)Q12N−121121()2222NNNNDBbb−−−−++++00(1)N01(2)1210()2222NNNFBbb−−−−−−−++++16SOPC16Q8216QQQ1510.9999695X−≤≤Q7256255.9921875X−≤≤Q1421.9999390X−≤≤Q6512511.9804375X−≤≤Q1343.9998779X−≤≤Q510241023.96875X−≤≤Q1287.9997559X−≤≤Q420482047.9375X−≤≤Q111615.9995117X−≤≤Q340966095.875X−≤≤Q103231.9990234X−≤≤Q281928191.75X−≤≤Q96463.9980469X−≤≤Q11638416383.5X−≤≤Q8128127.9960938X−≤≤Q03276832767X−≤≤x()qx(int)2Qqxx=×x()qx()2Qqxfloatx−=×17FPGASOPC183FPGASOPCFPGAIPSOPCFPGAIPSOPCFPGASOPC19QuartusII7.0FPGAFPGASOPCALTERALPMFPGA20FPGASOPC21SOPCFPGASOPC22FPGASOPC23FPGASOPC24FPGASOPC25FPGASOPCCycloneIIEP2C35FPGA2426FPGASOPC27FPGASOPC28LCD4112iTiiSample==∑29FPGADE2BoardFlashSDCardSDRAMUARTI2CLCDNiosIIFFTDCTMELFLASHSDSDRAMSRAMWM873130LCD4sMATLABSDYDTWNNLCDLCD31FPGA5FPGA25WM873132FPGA333R0(00H)4:016'h001A;11.5R1(01H)4:016'h021A;11.5R2(02H)6:016'h047B;11R3(03H)6:016'h067B;11R4(04H)2116'h0814;/ADC10R5(05H)2:11116'h0A06;1148KHZ1044.1KHZ0132KHZ00DisableR6(06H)8:016'h0C00;1:00111DSP10I2S01003:20011321024012000164DAC01DAC0DACR7(07H)6110001USB250/272fs0256/384fsUSBR8(08H)110250fs1272fs0256fs1384fsFPGA2734FPGAI2CIPCore35FPGAStart_WriteAUD_ADCDATclkSRAM_Address[14..0]WR_SRAMCE_SRAMOE_SRAMLB_SRAMUB_SRAMoAUD_BCKoAUD_LRCKSRAM_data[15..0]Unitary_SRAMinstRead_MAXB0001Start_UnitaryB0010UnitaryB0100Waite_UnitaryB1000fen6232side_count12Start_8731B001Save_DataB010WaiteB100ParameterValue3036FPGA32Fir1()10.9375Hzz−=−()()0.9375(1)ynxnxn=−−37FPGA3833FIR34FPGA3539FPGACLOCK_27CLOCK_50Write_ctrAddress_ctr[1..0]wCtr_data[15..0]Address_data[16..0]read_dataAUD_ADCDATrCtr_data[15..0]Read_Data[31..0]I2C_SCLKTD_RESETAUD_ADCLRCKAUD_DACLRCKAUD_BCLKAUD_XCKSRAM_ADDR[16..0]SRAM_CE_NSRAM_OE_NSRAM_LB_NSRAM_UB_NSRAM_WE_NI2C_SDATSRAM_DQ[15..0]Avalon_mulvadinst3637DMAMFCC40FPGA39MFCCFFTFFTFFT41FPGA40FFT41Q10256FFT42FPGA4()2561()()0.00059374=0.059%256iAiBiBi=−≈∑42FPGAMATLB43FPGAMEL()2595lg(1/700)Melff=+(5.1)43MELMATLAB44MEL2444FPGA45MelFPGA()000()()|kdfxx0fxdx=−xxx==∑(5.2)45FPGACORDIC1111111221,022(1,tanh(2)(12)0.5ln(12)iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiixxdyxxdyyyydxyydxdzzdzzd−−++−−++−−−++−⎧⎪⎧=+××=+××⎪−⎪⎧⎪=+××⇒=+××=⎨⎨+⎩⎪⎪=−×+⎩⎪=−××⎪−⎩)⎨(5.3)11121,02(1,(12)ln(12)iiiiiiiiiiiiiiiiixxdyyyydxdzzd−+−+−+−⎧⎪=+××⎪)−⎧⎪=+××=⎨+⎩⎪+⎪=−×⎪−⎩⎨n(5.4)ln()ntz=ln()ln(2)ln()ln(2)ln()0.6931nxttnt=×=+=+×(5.5)2nt×2nt×2t4≤46FPGA46CORDIC4747FPGA48MFCCclkadd_in_FFT[7..0]writewritedata[31..0]write_2writedata_2[7..0]address_2Address_A3[5..0]read_A3readdata[31..0]Read_DATA_A3[31..0]Avalon_MFCCinst149MFCC48FPGA50MATLAB51MFCC49FPGA5FAT1632(16)0x0~0x780x8~0xA30xB10xC~0x15100x16~0x1720x18~0x1920x1A~0x1B20x1C~0x1F452SD53DTW50FPGA54DTW51FPGAclkclk_endataa[31..0]datab[31..0]resetstartdoneresult[31..0]dist_cpu_1instdataa[31..0]datab[31..0]result[31..0]Which_is_Mininstclkclk_enresetstartdataa[31..0]datab[31..0]result[31..0]donefloat_addinstBig_or_SmallB0000001Too_BigB0000010ShiftB0000100AddB0001000Base_to_1B0010000FinishB0100000WaiteB1000000ParameterValueABCD55DTW52FPGAFPGA53FPGA54FPGAFrequency116.75MHZfmaxPCPCCPUInterPentiumD9403.2Ghz1024MbyteDDR2MATLAB6.5DE2PC3.2Ghz62msDE250Mhz27Mhz1.87ms33.2MFCC55FPGA59PCMATLAB6.5MFCCDE2PC3.2Ghz47msDE2MFCC50Mhz60us783DE2PC3.2Ghz2.45sDE250Mhz397ms6.256FPGA572252002588.8%225209693.3%4504093191.05%61244316972.3%2882167275.0%90065924173.2%FPGA605859606