第9章 基于VHDL的实用CPU创新设计

EDA技术与VHDL第9章基于VHDL的实用CPU创新设计9.1顶层系统设计9.1.116位CPU的组成结构图9-116位CPU结构框图2.顶层文件的原理图设计图9-2CPU顶层结构图（详细内容浏览）（1）运算器ALU运算器ALU的功能9.2基本硬件系统设计Sel输入操作说明0000C=A通过PASS0001C=AANDB与0010C=AORB或0011C=NOTA非0100C=AXORB异或0101C=A+B加法0110C=A–B减法0111C=A+1加11000C=A–1减11001C=0清0（1）运算器ALU运算器ALU结构图a[15..0]b[15..0]sel[3..0]c[15..0]aluinst9.2基本硬件系统设计6.2.1运算器ALU图6-5运算器ALU结构图6.2CPU基本部件设计libraryIEEE;useIEEE.std_logic_1164.all;useIEEE.std_logic_unsigned.all;usework.cpu_lib.all;entityaluisport(a,b:inbit16;sel:int_alu;c:outbit16);endalu;architecturertlofaluisbeginaluproc:process(a,b,sel)begincaseseliswhenalupass=c=aafter1ns;whenandOp=c=aandbafter1ns;whenorOp=c=aorbafter1ns;whenxorOp=c=axorbafter1ns;whennotOp=c=notaafter1ns;whenplus=c=a+bafter1ns;whenalusub=c=a-bafter1ns;wheninc=c=a+0000000000000001after1ns;whendec=c=a-0000000000000001after1ns;whenzero=c=0000000000000000after1ns;whenothers=c=0000000000000000after1ns;endcase;endprocess;endrtl;（1）运算器ALU运算器ALU的仿真波形⑴⑵⑶⑷⑸⑹⑺⑻⑼⑽⑾9.2基本硬件系统设计（2）运算器ALUALU运算仿真结果说明工作点波功能选择sel运算类型输入数据运算结果cab（1）0000通过PASS4567C=A,C=4567（2）0001与456723ACC=AANDB=4567∧23AC=0124（3）0010或456723ACC=AORB=4567∨23AC=67EF（4）0011非4567C=NOTA=BA98（5）0100异或4546723ACC=AXORB=A⊕B=4567⊕23AC=66CB（6）0101加法456723ACC=A+B=4567+23AC=6913（7）0110减法456735ACC=A–B=4567-35AC=0FBB（8）0111加14567C=A+1=4567+1=4568（9）1000减14567C=A–1=4567-1=4566（10）1001清0xxxxxxxxC=0000（11）1010~1111其它xxxxxxxxC=00009.2基本硬件系统设计（2）比较器COMP比较器的运算类型t_comp比较类型操作说明000eq(等于)若a=b，compout=1001neq(不等于)若ab，compout=1010gt(大于)若ab，compout=1011gte(大于等于)若a=b，compout=1100lt(小于)若ab，compout=1101lte(小于等于)若a=b，compout=1其他compout=09.2基本硬件系统设计6.2.2比较器COMP6.2CPU基本部件设计libraryIEEE;useIEEE.std_logic_1164.all;useIEEE.std_logic_arith.all;useIEEE.std_logic_unsigned.all;usework.cpu_lib.all;entitycompisport(a,b:inbit16；sel:int_comp；compout:outstd_logic)；endcomp;architecturertlofcompisbegincompproc:process(a,b,sel)begincaseseliswheneq=ifa=bthencompout='1'after1ns；elsecompout='0'after1ns；endif；whenneq=ifa/=bthencompout='1'after1ns;elsecompout='0'after1ns；endif；whengt=ifabthencompout='1'after1ns;elsecompout='0'after1ns；endif；whengte=ifa=bthencompout='1'after1ns；elsecompout='0'after1ns；endif;whenlt=ifabthencompout='1'after1ns；elsecompout='0'after1ns；endif;whenlte=ifa=bthencompout='1'after1ns；elsecompout='0'after1ns；endif;endcase；endprocess；endrtl；（2）比较器COMP比较器结构图a[15..0]b[15..0]sel[2..0]compoutcompinst9.2基本硬件系统设计（2）比较器COMP比较器COMP的仿真波形说明工作点波形功能选择sel比较类型t_comp输入数据比较运算结果compoutab（1）0等于357A357A∵a=b，∴compout=1（2）0等于357A1CD0∵ab，∴compout=0（3）1不等于357A357A∵a=b，∴compout=0（4）1不等于357AEB7C∵ab，∴compout=1（5）2大于357A1200∵ab，∴compout=1（6）2大于357A357A∵a=b，∴compout=0（7）2大于357A4689∵ab，∴compout=0（8）3大于等于357A1200∵ab，∴compout=1（9）3大于等于357A357A∵a=b，∴compout=1（10）3大于等于357A4689∵ab，∴compout=0（11）4小于357A1200∵ab，∴compout=0（12）4小于357A357A∵a=b，∴compout=0（13）4小于357A4689∵ab，∴compout=1（14）5小于等于357A1200∵ab，∴compout=0（15）5小于等于357A357A∵a=b，∴compout=1（16）~(17)6~7其他xxxxxxxxcompout=09.2基本硬件系统设计（2）比较器COMP比较器COMP的仿真波形图⑴⑵⑶⑷⑸⑹⑺⑻⑼⑽⑾⑿⒀⒁⒂⒃⒄9.2基本硬件系统设计（3）控制器CONTROL控制器CONTROL的实体结构图9.2基本硬件系统设计libraryIEEE;useIEEE.std_logic_1164.all;usework.cpu_lib.all;entitycontrolisport(clock，reset，ready，compout:instd_logic;instrReg:inbit16;progCntrWr，progCntrRd，addrRegWr，addrRegRd，outRegWr，outRegRd:outstd_logic;shiftSel:outt_shift;aluSel:outt_alu;compSel:outt_comp;opRegRd，opRegWr，instrWr，regRd，regWr，rw，vma:outstd_logic;regSel:outt_reg);endcontrol;architecturertlofcontrolissignalcurrent_state,next_state:state;begin（接下页）9.2基本硬件系统设计6.2CPU基本部件设计nxtstateproc:process(current_state,instrReg,compout,ready)beginprogCntrWr='0';progCntrRd='0';addrRegWr='0';outRegWr='0';outRegRd='0';shiftSel=shftpass;aluSel=alupass;compSel=eq;opRegRd='0';opRegWr='0';instrWr='0';regSel=000;regRd='0';regWr='0';rw='0';vma='0';casecurrent_stateiswhenreset1=aluSel=zeroafter1ns;shiftSel=shftpass;next_state=reset2;whenreset2=aluSel=zero;shiftSel=shftpass;outRegWr='1';next_state=reset3;whenreset3=outRegRd='1';next_state=reset4;whenreset4=outRegRd='1';addrRegRd='1';progCntrWr='1';addrRegWr='1';next_state=reset5;whenreset5=vma='1';rw='0';next_state=reset6;whenreset6=vma='1';rw='0';ifready='1'theninstrWr='1';next_state=execute;elsenext_state=reset6;endif;（接下页）6.2CPU基本部件设计whenexecute=caseinstrReg(15downto11)iswhen00000=next_state=incPc;--nopwhen00001=regSel=instrReg(5downto3);regRd='1';next_state=load2;when00010=regSel=instrReg(2downto0);regRd='1';next_state=store2;--storewhen00011=regSel=instrReg(5downto3);regRd='1';aluSel=alupass;shiftSel=shftpass;next_state=move2;when00100=progcntrRd='1';alusel=inc;shiftsel=shftpass;next_state=loadI2;when00101=progcntrRd='1';alusel=inc;shiftsel=shftpass;next_state=braI2;when00110=regSel=instrReg(5downto3);regRd='1';next_state=bgtI2;--BranchGTImmwhen00111=regSel=instrReg(2downto0);regRd='1';alusel=inc;shiftsel=shftpass;next_state=inc2;whenothers=next_state=incPc;（接下页）KX康芯科技6.2CPU基本部件设计endcase;whenload2=regSel=instrReg(5downto3);regRd=