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JEDECSTANDARDStress-Test-DrivenQualificationofIntegratedCircuitsJESD47I(RevisionofJESD47H.01,April2011)JULY2012JEDECSOLIDSTATETECHNOLOGYASSOCIATIONIC集成电路压力测试考核NOTICEJEDECstandardsandpublicationscontainmaterialthathasbeenprepared,reviewed,andapprovedthroughtheJEDECBoardofDirectorslevelandsubsequentlyreviewedandapprovedbytheJEDEClegalcounsel.JEDECstandardsandpublicationsaredesignedtoservethepublicinterestthrougheliminatingmisunderstandingsbetweenmanufacturersandpurchasers,facilitatinginterchangeabilityandimprovementofproducts,andassistingthepurchaserinselectingandobtainingwithminimumdelaytheproperproductforusebythoseotherthanJEDECmembers,whetherthestandardistobeusedeitherdomesticallyorinternationally.JEDECstandardsandpublicationsareadoptedwithoutregardtowhetherornottheiradoptionmayinvolvepatentsorarticles,materials,orprocesses.BysuchactionJEDECdoesnotassumeanyliabilitytoanypatentowner,nordoesitassumeanyobligationwhatevertopartiesadoptingtheJEDECstandardsorpublications.TheinformationincludedinJEDECstandardsandpublicationsrepresentsasoundapproachtoproductspecificationandapplication,principallyfromthesolidstatedevicemanufacturerviewpoint.WithintheJEDECorganizationthereareprocedureswherebyaJEDECstandardorpublicationmaybefurtherprocessedandultimatelybecomeanANSIstandard.Noclaimstobeinconformancewiththisstandardmaybemadeunlessallrequirementsstatedinthestandardaremet.Inquiries,comments,andsuggestionsrelativetothecontentofthisJEDECstandardorpublicationshouldbeaddressedtoJEDECattheaddressbelow,orreferto©JEDECSolidStateTechnologyAssociation20123103North10thStreetSuite240SouthArlington,VA22201-2107Thisdocumentmaybedownloadedfreeofcharge;howeverJEDECretainsthecopyrightonthismaterial.Bydownloadingthisfiletheindividualagreesnottochargefororreselltheresultingmaterial.PRICE:ContactJEDECPrintedintheU.S.A.AllrightsreservedPLEASE!DON’TVIOLATETHELAW!ThisdocumentiscopyrightedbyJEDECandmaynotbereproducedwithoutpermission.Forinformation,contact:JEDECSolidStateTechnologyAssociation3103North10thStreetSuite240SouthArlington,VA22201-2107orreferto(cont’d)STRESSDRIVENQUALIFICATIONOFINTEGRATEDCIRCUITSIC集成电路压力测试考核(FromJEDECBoardBallot,JCB-12-24,formulatedunderthecognizanceoftheJC14.3SubcommitteeonSiliconDevicesReliabilityQualificationandMonitoring.)通过JEDEC委员会JCB-12-24号投票，在JC14.3硅晶圆器件可靠性考核和监控小组委员会审理后系统地阐述和制定1Scope范围Thisstandarddescribesabaselinesetofacceptancetestsforuseinqualifyingelectroniccomponentsasnewproducts,aproductfamily,orasproductsinaprocesswhichisbeingchanged.这个文档描述了用于考核新产品、同族器件或工艺变更的可接受的基准测试标准Thesetestsarecapableofstimulatingandprecipitatingsemiconductordeviceandpackagingfailures.Theobjectiveistoprecipitatefailuresinanacceleratedmannercomparedtouseconditions.FailureRateprojectionsusuallyrequirelargersamplesizesthanarecalledoutinqualificationtesting.Forguidanceonprojectingfailurerates,refertoJESD85MethodsforCalculatingFailureRatesinUnitsofFITs.Thisqualificationstandardisaimedatagenericqualificationforarangeofuseconditions,butisnotapplicableatextremeuseconditionssuchasmilitaryapplications,automotiveunder-the-hoodapplications,oruncontrolledavionicsenvironments,nordoesitaddress2ndlevelreliabilityconsiderations,whichareaddressedinJEP150.Wherespecificuseconditionsareestablished,qualificationtestingtailoredtomeetthosespecificrequirementscanbedeveloped,usingJESD94thatwillresultinabetteroptimizationofresources.这些测试用于加速和诱发半导体器件和封装的失效。目的是通过比使用环境相比加速的方式来促成失效。相比考核测试，失效率的预测需要更多的样品数量。如果需要计算预期的失效率，请参考JESD85MethodsforCalculatingFailureRatesinUnitsofFITs。本考核标准用于制定一系列适用于一般使用环境下的通用考核标准，而不是用于例如军工应用，汽车电子，或者不受控的航天电子等极端使用环境；同时本标准也不解决JEP150标准中提出的2nd等级可靠性问题。在确定具体使用条件的情况下，可以使用JESD94开发适合于满足这些特定要求的考核测试，从而更好地优化测试资源。Thissetoftestsshouldnotbeusedindiscriminately.Eachqualificationprojectshouldbeexaminedfor:a)Anypotentialnewanduniquefailuremechanisms.b)Anysituationswherethesetests/conditionsmayinduceinvalidoroverstressfailures.注意：不要不加选择地使用本文档中的测试。应对每个考核项目进行确认：a）是否存在任何潜在的新的和独特的失效机制。b）任何测试或使用条件可能导致的失效或过应力失效情况。JEDECStandardNo.47IPage65.5Devicequalificationrequirements(cont’d)Ifitisknownorsuspectedthatfailureseitherareduetonewmechanismsorareuniquelyinducedbytheseverityofthetestconditions,thentheapplicationofthetestconditionasstatedisnotrecommended.Alternatively,newmechanismsoruniquelyproblematicstresslevelsshouldbeaddressedbybuildinganunderstandingofthemechanismanditsbehaviorwithrespecttoacceleratedstressconditions(Ref.JESD91,“MethodforDevelopingAccelerationModelsforElectronicComponentFailureMechanisms”andJESD94,“ApplicationSpecificQualificationusingKnowledgeBasedTestMethodology”).ConsiderationofPCboardassembly-leveleffectsmayalsobenecessary.Forguidanceonthis,refertoJEP150,Stress-Test-DrivenQualificationofandFailureMechanismsAssociatedwithAssembledSolidStateSurface-MountComponents.Thisdocumentdoesnotrelievethesupplieroftheresponsibilitytoassurethataproductmeetsthecompl