K4B4G1646Q-Samsung

-1-K4B4G1646QRev.0.5,Apr.2013SAMSUNGELECTRONICSRESERVESTHERIGHTTOCHANGEPRODUCTS,INFORMATIONANDSPECIFICATIONSWITHOUTNOTICE.Productsandspecificationsdiscussedhereinareforreferencepurposesonly.AllinformationdiscussedhereinisprovidedonanASISbasis,withoutwarrantiesofanykind.ThisdocumentandallinformationdiscussedhereinremainthesoleandexclusivepropertyofSamsungElectronics.Nolicenseofanypatent,copyright,maskwork,trademarkoranyotherintellectualpropertyrightisgrantedbyonepartytotheotherpartyunderthisdocument,byimplication,estoppelorother-wise.Samsungproductsarenotintendedforuseinlifesupport,criticalcare,medical,safetyequipment,orsimilarapplicationswhereproductfailurecouldresultinlossoflifeorpersonalorphysicalharm,oranymilitaryordefenseapplication,oranygovernmentalprocurementtowhichspecialtermsorprovisionsmayapply.ForupdatesoradditionalinformationaboutSamsungproducts,contactyournearestSamsungoffice.Allbrandnames,trademarksandregisteredtrademarksbelongtotheirrespectiveowners.2013SamsungElectronicsCo.,Ltd.Allrightsreserved.Preliminary4GbQ-dieDDR3LSDRAMOlnyx1696FBGAwithLead-Free&Halogen-Free(RoHScompliant)CAUTION:ThisdocumentincludessomeitemsstillunderdiscussioninJEDECTherefore,thosemaybechangedwithoutpre-noticebasedonJEDECprogress.Inaddition,itishighlyrecommendedthatyounotsendspecswithoutSamsung’spermission.datasheet1.35V-2-datasheetK4B4G1646QDDR3LSDRAMRev.0.5PreliminaryRevisionHistoryRevisionNo.HistoryDraftDateRemarkEditor0.5-PreliminarySPEC.ReleaseApr.2013-J.Y.Lee-3-datasheetK4B4G1646QDDR3LSDRAMRev.0.5PreliminaryTableOfContents4GbQ-dieDDR3LSDRAMOlnyx161.OrderingInformation.....................................................................................................................................................52.KeyFeatures.................................................................................................................................................................53.Packagepinout/MechanicalDimension&Addressing..................................................................................................63.1x16PackagePinout(Topview):96ballFBGAPackage........................................................................................63.2FBGAPackageDimension(x16).............................................................................................................................74.Input/OutputFunctionalDescription..............................................................................................................................85.DDR3SDRAMAddressing...........................................................................................................................................96.AbsoluteMaximumRatings..........................................................................................................................................106.1AbsoluteMaximumDCRatings...............................................................................................................................106.2DRAMComponentOperatingTemperatureRange................................................................................................107.AC&DCOperatingConditions.....................................................................................................................................107.1RecommendedDCoperatingConditions................................................................................................................108.AC&DCInputMeasurementLevels............................................................................................................................118.1AC&DCLogicinputlevelsforsingle-endedsignals..............................................................................................118.2VREFTolerances......................................................................................................................................................138.3AC&DCLogicInputLevelsforDifferentialSignals................................................................................................148.3.1.Differentialsignalsdefinition............................................................................................................................148.3.2.Differentialswingrequirementforclock(CK-CK)andstrobe(DQS-DQS)...................................................148.3.3.Single-endedrequirementsfordifferentialsignals...........................................................................................168.4DifferentialInputCrossPointVoltage......................................................................................................................178.5SlewratedefinitionforDifferentialInputSignals.....................................................................................................188.6SlewratedefinitionsforDifferentialInputSignals...................................................................................................189.AC&DCOutputMeasurementLevels....................................