IC电路设计

200536StateKeyLabofASIC&Systems,FudanUniversityStateKeyLabofASIC&Systems,FudanUniversity1FullCustom2Semi-Custom3(Programmable)StateKeyLabofASIC&Systems,FudanUniversityFullCustomFullCustom¾IC¾–––¾––“”StateKeyLabofASIC&Systems,FudanUniversityStateKeyLabofASIC&Systems,FudanUniversityFullCustomFullCustom¾–:T1T2T3T1T2T3–T1T2T3T1T2T1T2–T1T2T3–––CMOSStateKeyLabofASIC&Systems,FudanUniversityFullCustomFullCustom¾–IC––IC–––/ICStateKeyLabofASIC&Systems,FudanUniversityFullCustomFullCustomStateKeyLabofASIC&Systems,FudanUniversity1FullCustom2Semi-Custom3(Programmable)StateKeyLabofASIC&Systems,FudanUniversityICICCellCell--BasedICBasedIC¾CBICcell-basedIC⎯⎯⎯StandardCellMacroCore™™ALUA/DStateKeyLabofASIC&Systems,FudanUniversityICICCellCell--BasedICBasedIC¾¾¾–Aphysicallayout–Abehavioralmodel–AVerilog/VHDLmodel–Adetailedtimingmodel–Ateststrategy–Acircuitschematic–Acellicon–Awire-loadmodel–AroutingmodelStateKeyLabofASIC&Systems,FudanUniversityStateKeyLabofASIC&Systems,FudanUniversityICICCellCell--BasedICBasedIC–:–standardsizetransistors–doublesizetransistors–quadruplesizetransistors–sotoachievehighcircuitspeedandlayoutdensity–ROMRAMPLAStateKeyLabofASIC&Systems,FudanUniversityICICCellCell--BasedICBasedIC–80IC–EDA–RowsChannelsStateKeyLabofASIC&Systems,FudanUniversityICICCellCell--BasedICBasedIC¾ICStateKeyLabofASIC&Systems,FudanUniversityAsimplifiedAsimplifiedfloorplanfloorplanofstandardofstandard--cellscells--basedbasedStateKeyLabofASIC&Systems,FudanUniversitySimplifiedSimplifiedfloorplanfloorplanconsistingoftwoseparateconsistingoftwoseparateblocksandacommonsignalbusblocksandacommonsignalbusStateKeyLabofASIC&Systems,FudanUniversityICICCellCell--BasedICBasedIC¾Resuse–––StateKeyLabofASIC&Systems,FudanUniversityStateKeyLabofASIC&Systems,FudanUniversityastandardastandard--cellcell--basedchipwithasingleblockofcellsandbasedchipwithasingleblockofcellsandthreememorybanksthreememorybanksStateKeyLabofASIC&Systems,FudanUniversityICICCellCell--BasedICBasedIC¾–IC–ICStateKeyLabofASIC&Systems,FudanUniversityICICGateArrayICGateArrayIC¾MGAMaskedGateArrary:,¾¾CAD––StateKeyLabofASIC&Systems,FudanUniversityBasicprocessingstepsrequiredforGAimplementationBasicprocessingstepsrequiredforGAimplementationStateKeyLabofASIC&Systems,FudanUniversityICICGateArrayICGateArrayIC¾MGA–MGAIC–50%~60%–StateKeyLabofASIC&Systems,FudanUniversityICICGateArrayICGateArrayIC¾ChanneledGateArrary–ICIC––StateKeyLabofASIC&Systems,FudanUniversityMetalmaskdesigntorealizeacomplexlogicfunctiononachanneledGAplatformStateKeyLabofASIC&Systems,FudanUniversityStateKeyLabofASIC&Systems,FudanUniversityICICGateArrayICGateArrayIC¾SOGSeaofGateArray–––StateKeyLabofASIC&Systems,FudanUniversityTheplatformofaSeaTheplatformofaSea--ofof--Gates(SOG)chipGates(SOG)chipStateKeyLabofASIC&Systems,FudanUniversityComparisonbetweenthechanneled(GA)vs.theComparisonbetweenthechanneled(GA)vs.thechannellesschannelless(SOG)approaches(SOG)approachesStateKeyLabofASIC&Systems,FudanUniversityStateKeyLabofASIC&Systems,FudanUniversityICICGateArrayICGateArrayIC¾StructuredGateArray––••DSPStateKeyLabofASIC&Systems,FudanUniversityLayoutviewsofaconventionalGAchipandagatearraywithLayoutviewsofaconventionalGAchipandagatearraywithtwomemorybankstwomemorybanksStateKeyLabofASIC&Systems,FudanUniversityICICGateArrayICGateArrayIC¾–––•CBICMGAMGA•ICIP••MGA•StateKeyLabofASIC&Systems,FudanUniversity1FullCustom2Semi-Custom3(Programmable)StateKeyLabofASIC&Systems,FudanUniversityPLDPLD(ProgrammableLogicDevice)(ProgrammableLogicDevice)¾PLD–PLAProgrammableLogicArray–PALProgrammableArrayLogic–GALGeneralArrayLogic–PGAProgrammableGateArray–LCALogicCellArray¾PLD–“”“”–StateKeyLabofASIC&Systems,FudanUniversity¾–––SRAMStateKeyLabofASIC&Systems,FudanUniversityPLDPLD(ProgrammableLogicDevice)(ProgrammableLogicDevice)¾(Antituse)–FusePROMPLD–(100MΩ),(500Ω)–PROMEPROM–StateKeyLabofASIC&Systems,FudanUniversityPLD(ProgrammableLogicDevice)PLD(ProgrammableLogicDevice)¾–ActelACTFPGA–QuickLogicXlinx8100–XlinxCypressSRAMStateKeyLabofASIC&Systems,FudanUniversityPLD(ProgrammableLogicPLD(ProgrammableLogicDevice)Device)¾–EPROMEEPROM(FlashMemory)StateKeyLabofASIC&Systems,FudanUniversityPLD(ProgrammableLogicPLD(ProgrammableLogicDevice)Device)¾–––AlteraClassicMAXLaticeAMDXlinxCPLDFastFlashStateKeyLabofASIC&Systems,FudanUniversityPLD(ProgrammableLogicPLD(ProgrammableLogicDevice)Device)¾SRAM–SRAMSRAM–SRAMFPGASRAMStateKeyLabofASIC&Systems,FudanUniversityPLD(ProgrammableLogicPLD(ProgrammableLogicDevice)Device)¾SRAMStateKeyLabofASIC&Systems,FudanUniversityStateKeyLabofASIC&Systems,FudanUniversityPLD(ProgrammableLogicPLD(ProgrammableLogicDevice)Device)¾SRAM–SRAMSRAMASICPROMEPROM–SRAM6-7NMOSStateKeyLabofASIC&Systems,FudanUniversityPLD(ProgrammableLogicPLD(ProgrammableLogicDevice)Device)¾SRAM–SRAMASICPROMEPROMASICSRAMSRAM–SRAMASICXilinxFPGAAlteraFLEXAPEXAT&TDRCAActel(SPGA)SRAMStateKeyLabofASIC&Systems,FudanUniversity((FieldProgrammableGateFieldProgrammableGateArray)Array)¾PLDFPGAPLD¾FPGAPLD–PLA–PLD¾StateKeyLabofASIC&Systems,FudanUniversityFieldProgrammableGateArray(FPGA)Field