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第10章VerilogHDL高级程序设计3/20/20201MicroelectronicsSchoolXidianUniversity10.1乘法器设计3/20/20202MicroelectronicsSchoolXidianUniversity10.1.1Wallace树乘法器3/20/20203MicroelectronicsSchoolXidianUniversity部分积第1级第2级简单两输入加法器HAHAFAFAFAHAx3y3x3y2x2y3x2y2x1y3x3y1x1y2x0y3x3y0x2y1x1y1x0y2x2y0x1y0x0y1x0y0图10.1-2Wallace树乘法器结构图3/20/20204MicroelectronicsSchoolXidianUniversitymodulewallace(x,y,out);parametersize=4;//Defineparametersinput[size-1:0]x,y;output[2*size-1:0]out;//IOdeclarationwire[size*size-1:0]a;wire[1:0]b0,b1,c0,c1,c2,c3;//Wiredeclarationwire[5:0]add_a,add_b;wire[6:0]add_out;wire[2*size-1:0]out;assigna={x[3],x[3],x[2],x[2],x[1],x[3],x[1],x[0],x[3],x[2],x[1],x[0],x[2],x[1],x[0],x[0]}&{y[3],y[2],y[3],y[2],y[3],y[1],y[2],y[3],y[0],y[1],y[1],y[2],y[0],y[0],y[1],y[0]};//PrepartmultiplierhaddU1(.x(a[8]),.y(a[9]),.out(b0));//2inputhalfadderhaddU2(.x(a[11]),.y(a[12]),.out(b1));haddU3(.x(a[4]),.y(a[5]),.out(c0));faddU4(.x(a[6]),.y(a[7]),.z(b0[0]),.out(c1));//3inputfulladderfaddU5(.x(a[13]),.y(a[14]),.z(b0[1]),.out(c2));faddU6(.x(b1[0]),.y(a[10]),.z(b1[1]),.out(c3));assignadd_a={c3[1],c2[1],c1[1],c0[1],a[3],a[1]};//adderassignadd_b={a[15],c3[0],c2[0],c1[0],c0[0],a[2]};assignadd_out=add_a+add_b;assignout={add_out,a[0]};endmodule3/20/20205MicroelectronicsSchoolXidianUniversitymodulefadd(x,y,z,out);output[1:0]out;inputx,y,z;assignout=x+y+z;endmodulemodulehadd(x,y,out);output[1:0]out;inputx,y;assignout=x+y;endmodulemodulewallace_tb;reg[3:0]x,y;wire[7:0]out;wallacem(.x(x),.y(y),.out(out));//moduleinstanceinitial//Stimulisignalbeginx=3;y=4;#20x=2;y=3;#20x=6;y=8;endendmodule10.1.2复数乘法器3/20/20206MicroelectronicsSchoolXidianUniversity××××acbdadbcsub1sub2-add1add2+a*cb*da*db*c实部输出虚部输出3/20/20207MicroelectronicsSchoolXidianUniversity例10.1-1：用VerilogHDL设计实部和虚部均为4位2进制书的复数乘法器modulecomplex(a,b,c,d,out_real,out_im);input[3:0]a,b,c,d;output[8:0]out_real,out_im;wire[7:0]sub1,sub2,add1,add2;wallaceU1(.x(a),.y(c),.out(sub1));wallaceU2(.x(b),.y(d),.out(sub2));wallaceU3(.x(a),.y(d),.out(add1));wallaceU4(.x(b),.y(c),.out(add2));assignout_real=sub1-sub2;assignout_im=add1+add2;endmodulemodulecomplex_tb;reg[3:0]a,b,c,d;wire[8:0]out_real;wire[8:0]out_im;complexU1(.a(a),.b(b),.c(c),.d(d),.out_real(out_real),.out_im(out_im));initialbegina=2;b=2;c=5;d=4;#10a=4;b=3;c=2;d=1;#10a=3;b=2;c=3;d=4;endendmodule10.1.3向量乘法器3/20/20208MicroelectronicsSchoolXidianUniversitya1b1a2b2a3b3a4b4+++out3/20/20209MicroelectronicsSchoolXidianUniversity例10.1-2：用VerilogHDL设计一个4维向量乘法器modulevector(a1,a2,a3,a4,b1,b2,b3,b4,out);input[3:0]a1,a2,a3,a4,b1,b2,b3,b4;outputwire[9:0]out;wire[7:0]out1,out2,out3,out4;wire[8:0]out5,out6;wallacem1(.x(a1),.y(b1),.out(out1));wallacem2(.x(a2),.y(b2),.out(out2));wallacem3(.x(a3),.y(b3),.out(out3));wallacem4(.x(a4),.y(b4),.out(out4));assignout5=out1+out2;assignout6=out3+out4;assignout=out5+out6;endmodulemodulevector_tb;reg[3:0]a1,a2,a3,a4;reg[3:0]b1,b2,b3,b4;wire[9:0]out;initialbegina1=2’b10;a2=2’b10;a3=2’b10;a4=2’b10;b1=2’b10;b2=2’b10;b3=2’b10;b4=2’b10;endvectorm(.a1(a1),.a2(a2),.a3(a3),.a4(a4),.b1(b1),.b2(b2),.b3(b3),.b4(b4),.out(out));endmodule10.1.4查找表乘法器3/20/202010MicroelectronicsSchoolXidianUniversity表10.1-12×2位的乘法查找表00011011000000000000000000010000000100100011100000001001000110110000001101101001modulelookup(out,a,b,clk);output[3:0]out;input[1:0]a,b;inputclk;reg[3:0]out;reg[3:0]address;always@(posedgeclk)beginaddress={a,b};case(address)4'b0000:out=4'b0000;4'b0001:out=4'b0000;4'b0010:out=4'b0000;4'b0011:out=4'b0000;4'b0100:out=4'b0000;4'b0101:out=4'b0001;4'b0110:out=4'b0010;4'b0111:out=4'b0011;4'b1000:out=4'b0000;4'b1001:out=4'b0010;4'b1010:out=4'b0100;4'b1011:out=4'b0110;4'b1100:out=4'b0000;4'b1101:out=4'b0011;4'b1110:out=4'b0110;4'b1111:out=4'b1001;default:out=4'bx;endcaseendendmodule3/20/202011MicroelectronicsSchoolXidianUniversitymodulelookup_mult(out,a,b,clk);output[7:0]out;input[3:0]a,b;inputclk;reg[7:0]out;reg[1:0]firsta,firstb,seconda,secondb;wire[3:0]outa,outb,outc,outd;always@(posedgeclk)beginfirsta=a[3:2];seconda=a[1:0];firstb=b[3:2];secondb=b[1:0];endlookupm1(.out(outa),.a(firsta),.b(firstb),.clk(clk));lookupm2(.out(outb),.a(firsta),.b(secondb),.clk(clk));lookupm3(.out(outc),.a(seconda),.b(firstb),.clk(clk));lookupm4(.out(outd),.a(seconda),.b(secondb),.clk(clk));always@(posedgeclk)beginout=(outa4)+(outb2)+(outc2)+outd;endendmodulemodulelookup_mult_tb;reg[3:0]a,b;regclk=0;wire[7:0]out;integeri,j;always#10clk=~clk;lookup_multm1(.out(out),.a(a),.b(b),.clk(clk));initialbegina=0;b=0;for(i=1;i15;i=i+1)#20a=i;endinitialbeginfor(j=1;j15;j=j+1)#20b=j;endinitialbegin#360$stop;endendmodule10.2FIFOVerilogHDL实现3/20/202012MicroelectronicsSchoolXidianUniversityCell6Cell5Cell4Cell3Cell2Cell1Cell0Cell7写指针读指针Cell6Cell5Cell4Cell3Cell2Cell1Cell0Cell7写指针读指针Cell6Cell5Cell4Cell3Cell2Cell1Cell0Cell7写指针读指针Cell6Cell5Cell4Cell3Cell2Cell1Cell0Cell7写指针读指针A.一个空堆栈B.写入一个数据C.写入七次数据之后D.堆栈满addr_inaddr_outqdwerdclkwrite_ptrread_ptrwrite_to_stackread_from_stackclkrststack_fullstack_emptyData_inwrite_to_stack3/20/202013MicroelectronicsSchoolXidi