曼彻斯特编码的verilog实现

modulebianma(din,rst,clk16x,clk96,start,tx,sr,state,clk_en,man);inputrst,clk16x,start;input[7:0]din;outputtx,clk96,sr,state,clk_en,man;regclk_en;reg[7:0]sr;regclk96;regtx,man;reg[3:0]state;reg[2:0]cnt;always@(posedgeclk16x)begincnt=cnt+1;if(cnt==7)clk96=~clk96;endalways@(negedgeclk16xornegedgestartorposedgerst)beginif(rst)beginclk_en=1'd0;endelseif(!start)beginclk_en=1'b1;endelseif(state==4'd12)beginclk_en=1'b0;endendalways@(negedgeclk96orposedgerst)beginif(rst)begintx=1'b1;sr=8'b0;endelseif(state==4'd1)beginsr=din;endelseif(state==4'd2)begintx=1'b0;endelseif((state=4'd3)&&(state=4'd10))begintx=sr[0];sr[6:0]=sr[7:1];sr[7]=1'b1;endelseif(state==4'd11)begintx=1'b1;endelsetx=1'b1;endalwaysbeginif((state=4'd3)&&(state=4'd10))beginman=tx^clk96;endelseman=1'b0;endalways@(posedgeclk96orposedgerstornegedgeclk_en)beginif(rst)state=4'b0000;elseif(!clk_en)state=4'b0000;elsestate=state+1;endendmodule