pg109-xfft

FastFourierTransformv9.0LogiCOREIPProductGuideVivadoDesignSuitePG109April1,2015FastFourierTransformv9.0:OverviewLicensingandOrderingInformation...................................................6Chapter2:ProductSpecificationResourceUtilization................................................................7PortDescriptions..................................................................7Chapter3:DesigningwiththeCoreClocking.........................................................................11Resets..........................................................................11EventSignals.....................................................................12AXI4-StreamConsiderations........................................................13TheoryofOperation..............................................................28Chapter4:DesignFlowStepsCustomizingandGeneratingtheCore................................................58SystemGeneratorforDSPGraphicalUserInterface.....................................65ConstrainingtheCore.............................................................66Simulation......................................................................66SynthesisandImplementation......................................................67Chapter5:CModelFeatures........................................................................68Overview.......................................................................68UnpackingandModelContents.....................................................69Installation......................................................................69SoftwareRequirements............................................................70FFTCModelInterface.............................................................70CModelExampleCode............................................................76CompilingwiththeFFTCModel.....................................................77FFTMATLABSoftwareMEXFunction.................................................78SendFeedbackFastFourierTransformv9.0:DetailedExampleDesignDemonstrationTestBench.........................................................84AppendixA:MigratingandUpgradingMigratingtotheVivadoDesignSuite.................................................87UpgradingintheVivadoDesignSuite................................................87AppendixB:DebuggingFindingHelponXilinx.com.........................................................92DebugTools.....................................................................93SimulationDebug.................................................................95InterfaceDebug..................................................................95AppendixC:AdditionalResourcesandLegalNoticesXilinxResources..................................................................96References......................................................................96RevisionHistory..................................................................97PleaseRead:ImportantLegalNotices................................................97SendFeedbackFastFourierTransformv9.0®LogiCORE™IPFastFourierTransform(FFT)implementstheCooley-TukeyFFTalgorithm,acomputationallyefficientmethodforcalculatingtheDiscreteFourierTransform(DFT).Features•ForwardandinversecomplexFFT,runtimeconfigurable•TransformsizesN=2m,m=3–16•Datasampleprecisionbx=8–34•Phasefactorprecisionbw=8–34•Arithmetictypes:°Unscaled(full-precision)fixed-point°Scaledfixed-point°Blockfloating-point•Fixed-pointorfloating-pointinterface•Roundingortruncationafterthebutterfly•BlockRAMorDistributedRAMfordataandphase-factorstorage•Optionalruntimeconfigurabletransformpointsize•Runtimeconfigurablescalingscheduleforscaledfixed-pointcores•Bit/digitreversedornaturaloutputorder•Optionalcyclicprefixinsertionfordigitalcommunicationssystems•Fourarchitecturesofferatrade-offbetweencoresizeandtransformtime•BitaccurateCmodelandMEXfunctionforsystemmodelingavailablefordownloadIPFactsLogiCOREIPFactsTableCoreSpecificsSupportedDeviceFamily(1)UltraScale™Architecture,Zynq®-7000,7SeriesSupportedUserInterfacesAXI4-StreamResourcesSeeResourceUtilizationProvidedwithCoreDesignFilesEncryptedRTLExampleDesignNotProvidedTestBenchVHDLConstraintsFileNotProvidedSimulationModelEncryptedVHDLCModelSupportedS/WDriverN/ATestedDesignFlows(2)DesignEntryVivado®DesignSuiteSystemGeneratorforDSPSimulationForsupportedsimulators,seetheXilinxDesignTools:ReleaseNotesGuide.SynthesisVivadoSynthesisSupportProvidedbyXilinx@:1.Foracompletelistingofsupporteddevices,seetheVivadoIPcatalog.2.Forthesupportedversionsofthetools,seetheXilinxDesignTools:ReleaseNotesGuide.SendFeedbackFastFourierTransform