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DSPFPGA邬诚,周贵良,郭波,陈列(南京电子技术研究所,江苏省南京市210039):主要介绍了一种基于PC+DSP+FPGA体系结构的多雷达脉冲信号模拟器,能够模拟1~4部常规雷达重频抖动雷达重频参差雷达重频参差抖动雷达频率捷变雷达等多种体制雷达的混叠脉冲信号,并提供对应的载频编码输出,仿真度高雷达的部数及每部雷达的参数可通过主控计算机中的主控软件进行设置,使用方便灵活,信号通用性强该系统可在电子战设备前端微波分系统不参与的条件下,为后级数据处理分系统调试提供逼真的雷达测试信号:雷达脉冲;模拟器;TMS320LF2407;XC2S200:TN952收稿日期:20092122190引言,,,,,,,DSPFPGA,PC+DSP+FPGAFPGA,,,,,,1多雷达脉冲信号模拟器工作原理,,[122]kPRIk,pri1)():PRIk=pri(1)2):N,pri0,pri1,,,priN-1PRIk=prii(i=k%N)(2)3):$pri,pri,rand(-$pri,$pri)[-$pri,$pri]PRIk=pri+rand(-$pri,$pri)(3)4):PRIk=prii+rand(-$pri,$pri)(4),,,,k:Fk=f+rand(-$f,$f)(5):f;$f,DSPFPGA,PC+DSP+FPGA,1PC,,RS2232DSP,DSP,FP2GAFPGA,FPGA,#12#36220102InformatizationResearchVo.l36No.2Feb.201012硬件电路的设计与实现:DSPFPGARS22322.1运算及主控模块DSPTIC2000TMS320LF2407[3],LF2407,PC,FPGA,LF2407FPGA,,FPGARAM,Crand(),FPGA,DSP,DSPFPGARAM,/0DSP20MHz,DSP32,16,FPGA/0100ns,:(0.2Ls~100ms),(0.1Ls~1000Ls),(1~16)2.2信号产生模块,FPGAFPGAXilinxXC2S200[4],40MHz32.2.1DSP4,8,,,,XC2S200,FPGA432,8RAM,RAM,RAM32,NN(N[8),0x000,LF240716,32,1616,DSPFPGA216,32RAM322.2.22/0RAM,CTRDSP,CTR=c0c,RAMDSP,DSPRAM,DSPRAM,CTR=c1c,FPGA,FPGARAMFPGARAMFPGA_A[2B0]FP2GA_RD/FPGA0/FPGA0,,,32/FPGA0FPGARAM,CTRFPGA,0x000,/0,1,SIZE[2B0]1,DSPSIZE[2B0],0x000,3,100nsFPGA_RD50ns,/-+/-.0RAMRAM#13#362,:DSPFPGA##3,/FPGA0,/0,DSPSEED[31B0],25ns32IP32,425ns,(M[31B0]+1),100ns(0,M[31B0]]RANDOM[31B0],M[31B0]DSP,0,0,/-+/-.0,RRI.[31B0],PRI[31B0]RANDOM[31B0],/+0/-0,/0OPERATOR,OP2ERATOR=0,,OPERATOR=1,,RRI.[31B0],/0,3/0,32,CTRFPGA,,10MHz100ns,0,/-+/-.0PRI.[31B0]-1,PW[31B0]-10,,,PRI.[31B0]@100nsPW[31B0]@100ns4/0,DSP,32.2.3,/0(0,deltaF[15B0]],DSP,deltaF[15B0],,,,,,,,,,(16c1c)4,flagn(n=1,2,3,4)4,c1c,c0cflagflag4flag3flag2flag14,flag=/00000,flagSOR4S1S2S3S4/0,4#14###201023结束语XC2S200FP2GA,,,,,,,,,,[1].[M].:,1999:86289.[2],.[M].3.:,2002:25248.[3],,,.TMS320LF240XDSPC[M].:,2003.[4]XilinxInc.Spartan2IIFPGAFamilyDataSheet[EB/OL].2008206213.邬诚(19812),男,硕士研究生,主要研究方向为雷达对抗信号处理雷达信号分选DesignofMultipleKindRadarPulseSignalSimulatorBasedonDSPandFPGAWUCheng,ZHOUGuiliang,GUOBo,CHENLie(NanjingResearchInstituteofElectronicsTechnology,Nanjing210039,China)Abstract:AmultiplekindradarpulsesignalsimulatorbasedonPC+DSP+FPGAsystemisintroducedinthispaper.Thissimulatorcansimulateinterleavedpulsesignalsof1~4kindsofradars,includingPRFjitteringradar,PRFstaggeringradar,PRFstaggeringjitteringradarandfrequencyagilityradar,etc.Italsoprovidesoutputofcarrierfrequencycodecorrespondingly.ThenumberandparametersofradarscanbesetinthecontrolsoftwareonthePC.Therefore,thissystemhastheadvantagesofflexibilityanduniversalness.Thissystemcanproviderealisticradartestsignalsfordebuggingsecondarydataprocessingsubsystemwhentheelectronicwarfareequipmentisnotpossessedofmicrowavesubsystem.Keywords:radarpulse;simulator;TMS320LF2407;XC2S200(上接第7页)IPHeadCompressionandItsPerformanceinWCDMAYINYuan(CollegeofJincheng,NanjingUniversityofAeronauticsandAstronautics,Nanjing211156,China)Abstract:Withthedevelopmentofwirelesscommunicationtechniques,therehasbeenanever2increasingdemandforallkindsofdataservices,whichmakesthealreadylimitedspectrumamorescarceresource.IPheadcompressionisatechniquethatleadstolessbandwidthrequirementsbycompressingthefixedandredun2dantpartinIPpackets.Inthispaper,wefirstelaboratetheexistingIPheadcompressionalgorithms(CRTPandROCCO),andthencomparetheirperformanceintheWCDMAsystemthroughsimulationsoverthetypicalwirelesschannels.SimulationresultsshowthatROCCOismorerobusttotransmissionerrorsthanCRTP.Withthehighcompressionrate,ROCCOdramaticallydecreasetheprobabilityofpacketloss,andhenceisabetterchoiceforreal2timeserviceinwirelesscommunications.Keywords:IP/TCP/UDP/RTPpacke;tCRTP;ROCCO;compressionanddecompression;BER#15#362,:DSPFPGA##