clock-switch-glitch-free

WhitePaperTechniquestoMakeClockSwitchingGlitchFreeAugust2003,ver.1.01WP-CLCKSWTCH-1.0Withmoreandmoremulti-frequencyclocksbeingusedintoday’sdevicesespeciallyinthecommunicationsfielditisoftennecessarytoswitchthesourceofaclocklinewhilethedeviceisrunning.Thissourceswitchingisusuallyimplementedbymultiplexingtwodifferentfrequencyclocksourcesinhardwareandcontrollingthemultiplexerselectlinebyinternallogic.Thetwoclockfrequenciescanbetotallyunrelatedtoeachotherortheycanbemultiplesofeachother.Ineithercase,thereisachanceofgeneratingaglitchontheclocklineatthetimeoftheswitch.Aglitchontheclocklineishazardoustothewholesystem,asitcouldbeinterpretedasacaptureclockedgebysomeregisterswhilemissedbyothers.Thiswhitepaperdiscussestwodifferentmethodsofavoidingaglitchattheoutputclocklineofaswitch.Thefirstmethodisusedwhenclocksaremultiplesofeachother;thesecondmethodshowsclocksthataretotallyunrelatedtoeachother.On-the-FlyClockSwitchingProblemsThemultiplexerhasonecontrolsignal,SELECT,whicheitherpropagatesCLK0totheoutputwhensetto“zero”orpropagatesCLK1totheoutputwhensetto“one.”WhentheSELECTvaluechanges,aglitchcanoccurduetoimmediateswitchingoftheoutputfromthecurrentclocksourcetothenextclocksource.Thecurrentclockistheclocksourcecurrentlyselected;thenextclockistheclocksourcecorrespondingtothenewSELECTvalue.ThetimingdiagraminFigure1showshowaglitchisgeneratedattheoutput,OUTCLOCK,whentheSELECTcontrolsignalchanges.Theproblemwiththiskindofswitchisthattheswitchcontrolsignalcanchangeatanytimewithrespecttothesourceclocks,thuscreatingapotentialforremovingtheoutputclockorcreatingaglitchattheoutput.Theselectcontrolsignalismostlikelygeneratedbyaregisterdrivenbyeitherofthetwosourceclocks,meaningthateitherithasaknowntimingrelationshiptobothclocks(ifbothclocksaremultiplesofeachother),oritcanbeasynchronoustoatleastoneclock(ifsourceclocksarenotrelatedinanyway).Youmustavoidswitchingduringeitherclock’shighstatewithouthavinganyknowledgeaboutthefrequenciesorphaserelationshipsoftheseclocks.Youcanuseafixeddelaytoinducethegapbetweenthestartandstoptimeofthetwosourceclocks,butonlyifafixedrelationshipexistsbetweenthetwoclocksources.Itcannotbeusedwhereeitheroneoftheinputfrequenciesisnotknown,orwhentheclocksarenotrelated.TechniquestoMakeClockSwitchingGlitchFreeAlteraCorporation2Figure1showsasimpleimplementationofaclockswitch,usinganAND/OR-typemultiplexerlogic.Figure1.ClockSwitchingMultiplexerGlitchProtectionforRelatedClockSourcesFigure2showshowtopreventaglitchattheoutputofaclockswitchwheresourceclocksaremultiplesofeachother.AnegativeedgetriggeredD-typeflipflopisinsertedintheselectionpathforeachoftheclocksources.Registeringtheselectioncontrolatthenegativeedgeoftheclock,alongwithinitiallyenablingtheselectionaftertheotherclockisde-selected,providesexcellentprotectionagainstoutputglitches.Registeringtheselectsignalatthenegativeedgeoftheclockguaranteesthatnochangesoccurattheoutputwhileeitheroftheclocksareatahighlevel,thusprotectingagainstremovingtheoutputclock.Feedbackfromoneclock’sselectiontotheotherenablestheswitchtowaitforde-selectionofthecurrentclockbeforestartingthepropagationofthenextclock,avoidinganyglitches.AlteraCorporationTechniquestoMakeClockSwitchingGlitchFree3Figure2showshowthetransitionoftheSELECTsignalfrom0to1firststopspropagationofCLK0totheoutputattheproceedingfallingedgeofCLK0,thenstartsthepropagationofCLK1totheoutputatthefollowingnegativeedgeofCLK1.Therearethreetimingpathsinthiscircuitthatneedspecialconsideration—theSELECTcontrolsignaltoeitheroneofthetwonegative-edgetriggeredflipflops,theoutputofDFF0toinputofDFF1,andtheoutputofDFF1totheinputofDFF0.Ifthesignalonanyofthesethreepathschangesatthesametimeasthecapturingedgeofthedestinationflipflop’sclock,thereisasmallchancethattheoutputofthatregistercanbecomemeta-stable,meaningitcangotoastatebetweenanideal“one”andanideal“zero.”Ameta-stablestatecanbeinterpreteddifferentlybytheclockmultiplexerandtheenablefeedbackoftheotherflipflop.Therefore,itisrequiredthatcapturingedgesofbothflipflopsandthelaunchedgeoftheSELECTsignalshouldbesetapartfromeachothertoavoidanyasynchronousinterfacing.Thiscanbeeasilyaccomplishedbyusingthepropermulti-cycleholdconstraintsorminimumdelayconstraints,asthetimingrelationshipisknownbetweenthetwoclocks.TechniquestoMakeClockSwitchingGlitchFreeAlteraCorporation4Figure2.Glitch-FreeClockSwitchingforRelatedClocksFaultToleranceAtthedevicestart-uptime,bothflipflops(DFF0andDFF1)shouldberesettothe“zero”statesothatneitheroneoftheclocksisinitiallypropagated.Bystartingbothflipflopsina“zero”state,faulttoleranceisbuiltintotheclockswitch.AlteraCorporationTechniquestoMakeClockSwitchingGlitchFree5Forexample,oneoftheclockswasnottogglingduetoafaultatstart-uptime.Iftheflipflopassociatedwiththefaultyclockhadstartedupin“one”state,itwouldpreventtheselectionoftheotherclockasthenextclock,anditsownstatecannotbechangedduetolackofarunningclock.Bystartingbothflipflopsin“zero”state,evenifoneofthesourceclocksisnotrunning,youcanstillpropagatetheothergoodclocktotheoutputoftheswitch.GlitchProtectionforUnrelatedClockSourcesThep