东南大学CPU设计报告(附源程序vhdl)

ComputerOrganizationandArchitectureCourseDesignMicroprogrammedCPUDesignSchoolofInformationScienceandEngineeringSoutheastUniversity2012-04-07CPUReport—040091CONTENTS1.Purpose............................................................................................................................22.Tasks.....................................................................................................................................22.1InstructionSet................................................................................................................2Table1Listofinstructionsandrelevantopcodes2.2InternalRegistersandMemory.................................................................................32.3ALU....................................................................................................................................3Table2ALUOperations2.4MicroprogrammedControlUnit................................................................................4Table3ThemeaningofeachbitofthemicroinstructionTable4TheSequenceofMicroinstructions(appendix)Table5Themeaningofeachbitofthe8-bitflag.3.Top-LevelStructure.............................................................................................63.1Symbolsofinternalregisters,ALU,CUandmemory..............................................63.2Top-LevelStructureofCPU...........................................................................................74.TheSimulationInputWaveforms.....................................................105.Test........................................................................................................................................9Testproblem1:testLOAD,STORE,AND,SHR,SHL,SAR,SAL.................................9Table7Testofprogramofproblem1Testproblem2:testSUB,ADD,JMPGEZ,HALT.........................................................11Table8Testofprogramtocalculate1+2+……100Testproblem3:testJMP,MPY,OR,NOT.....................................................................13Table9Testofprogramtocalculate（（543-800）3）OR（（543+125））,not5436.ConclusionsandDiscussions..................................................................167.Appendix.......................................................................................................................17CPUReport—040092MicroprogrammedCPUDesign1.Purpose:ThepurposeofthisprojectistodesignasimpleCPU(CentralProcessingUnit).ThisCPUhasbasicinstructionset,andwewillutilizeitsinstructionsettogenerateaverysimpleprogramtoverifyitsperformance.Forsimplicity,wewillonlyconsidertherelationshipamongtheCPU,registers,memoryandinstructionset.Thatistosayweonlyneedconsiderthefollowingitems:Read/WriteRegisters,Read/WriteMemoryandExecutetheinstructions.2.Tasks:AtleastfourpartsconstituteasimpleCPU:theinstructionset,theinternalregisters,theALUandthecontrolunit.2.1InstructionSetSingle-addressinstructionformatisusedinmysimpleCPUdesign.Theinstructionwordcontainstwosections:theoperationcode(opcode),whichdefinesthefunctionofinstructions(addition,subtraction,logicoperations,etc.);theaddresspart,inmostinstructions,theaddresspartcontainsthememorylocationofthedatumtobeoperated,wecalleditdirectaddressing.Insomeinstructions,theaddresspartistheoperand,whichiscalledimmediateaddressing.Table1ListofinstructionsandrelevantopcodesINSTRUCTIONOPCODE(BIN)OPCODE(HEX)COMMENTSSTOREX0000000101ACC→[X]LOADX0000001002[X]→ACCADDX0000001103ACC+[X]→ACCSUBX0000010004ACC−[X]→ACCJMPGEZX0000010105IfACC≥0X→PC,elsePC+1→PCJMPX0000011006X→PCHALT0000011107HaltaprogramMPYX0000100008ACC×[X]→ACC,MRDIVX0000100109ACC÷[X]→ACC,DRANDX000010100AACCand[X]→ACCORX000010110BACCor[X]→ACCNOTX000011000CNOT[X]→ACCSHR000011010DACC1→ACCSHL000011100EACC1→ACCSAR000011110FACC/2→ACCSAL0001000010ACC*2→ACCCPUReport—0400932.2InternalRegistersandMemoryMAR(MemoryAddressRegister)MARcontainsthememorylocationofthewordtobereadfromthememoryorwrittenintothememory.Here,READoperationisdenotedastheCPUreadsfrommemory,andWRITEoperationisdenotedastheCPUwritestomemory.Inmydesign,MARhas8bitstoaccessoneof256addressesofthememory.MBR(MemoryBufferRegister)MBRcontainsthevaluetobestoredinmemoryorthelastvaluereadfrommemory.MBRisconnectedtotheaddresslinesofthesystembus.Inmydesign,MBRhas16bits.PC(ProgramCounter)PCkeepstrackoftheinstructionstobeusedintheprogram.Inmydesign,PChas8bits.IR(InstructionRegister)IRcontainstheopcodepartofaninstruction.Inmydesign,IRhas8bits.BR(BufferRegister)BRisusedasaninputofALU,itholdsotheroperandforALU.Inmydesign,BRhas16bits.ACC(Accumulator)ACCholdsoneoperandforALU,andgenerallyACCholdsthecalculationresultofALU.Inmydesign,ACChas16bits.Inthisdesignment,ACCissetinALUforsimplification.MR(MultiplierRegister)MRisusedforimplementingtheMPYinstruction,holdingthemultiplieratthebeginningoftheinstruction.Whentheinstructionisexecuted,itholdspartoftheproduct(thehighpartofthe32-bitproduct).LPM_RAM_DQLPM_RAM_DQisaRAMwithseparateinputandoutputports,itworksasmemory,anditssizeis256×16.Althoughit’snotaninternalregisterofCPU,weneedittosimulateandt