搜索
第3章VHDL基础3-1：画出与下例实体描述对应的原理图符号元件：ENTITYbuf3sIS--实体1：三态缓冲器PORT(input:INSTD_LOGIC;--输入端enable:INSTD_LOGIC;--使能端output:OUTSTD_LOGIC);--输出端ENDbuf3x;ENTITYmux21IS--实体2：2选1多路选择器PORT(in0,in1,sel:INSTD_LOGIC;output:OUTSTD_LOGIC);3-1.答案3-2.图3-30所示的是4选1多路选择器，试分别用IF_THEN语句和CASE语句的表达方式写出此电路的VHDL程序。选择控制的信号s1和s0的数据类型为STD_LOGIC_VECTOR；当s1='0'，s0='0'；s1='0'，s0='1'；s1='1'，s0='0'和s1='1'，s0='1'分别执行y=a、y=b、y=c、y=d。3-2.答案LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYMUX41ISPORT(s:INSTD_LOGIC_VECTOR(1DOWNTO0);--输入选择信号a,b,c,d:INSTD_LOGIC;--输入信号y:OUTSTD_LOGIC);--输出端ENDENTITY;ARCHITECTUREARTOFMUX41ISBEGINPROCESS(s)BEGINIF(S=00)THENy=a;ELSIF(S=01)THENy=b;ELSIF(S=10)THENy=c;ELSIF(S=11)THENy=d;ELSEy=NULL;ENDIF;EDNPROCESS;ENDART;LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYMUX41ISPORT(s:INSTD_LOGIC_VECTOR(1DOWNTO0);--输入选择信号a,b,c,d:INSTD_LOGIC;--输入信号y:OUTSTD_LOGIC);--输出端ENDMUX41;ARCHITECTUREARTOFMUX41ISBEGINPROCESS(s)BEGINCASEsISWHEN“00”=y=a;WHEN“01”=y=b;WHEN“10”=y=c;WHEN“11”=y=d;WHENOTHERS=NULL;ENDCASE;ENDPROCESS;ENDART;3-3.图3-31所示的是双2选1多路选择器构成的电路MUXK，对于其中MUX21A，当s='0'和'1'时，分别有y='a'和y='b'。试在一个结构体中用两个进程来表达此电路，每个进程中用CASE语句描述一个2选1多路选择器MUX21A。3-3.答案LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYMUX221ISPORT(a1,a2,a3:INSTD_LOGIC_VECTOR(1DOWNTO0);--输入信号s0,s1:INSTD_LOGIC;outy:OUTSTD_LOGIC);--输出端ENDENTITY;ARCHITECTUREONEOFMUX221ISSIGNALtmp:STD_LOGIC;BEGINPR01:PROCESS(s0)BEGINIFs0=”0”THENtmp=a2;ELSEtmp=a3;ENDIF;ENDPROCESS;PR02:PROCESS(s1)BEGINIFs1=”0”THENouty=a1;ELSEouty=tmp;ENDIF;ENDPROCESS;ENDARCHITECTUREONE;ENDCASE;3-4.下图是一个含有上升沿触发的D触发器的时序电路，试写出此电路的VHDL设计文件。3-4.答案LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYMULTIISPORT(CL:INSTD_LOGIC;--输入选择信号CLK0:INSTD_LOGIC;--输入信号OUT1:OUTSTD_LOGIC);--输出端ENDENTITY;ARCHITECTUREONEOFMULTIISSIGNALQ:STD_LOGIC;BEGINPR01:PROCESS(CLK0)BEGINIFCLK‘EVENTANDCLK=’1’THENQ=NOT(CLORQ);ELSEENDIF;ENDPROCESS;PR02:PROCESS(CLK0)BEGINOUT1=Q;ENDPROCESS;ENDARCHITECTUREONE;ENDPROCESS;3-5.给出1位全减器的VHDL描述。要求：(1)首先设计1位半减器，然后用例化语句将它们连接起来，图3-32中h_suber是半减器，diff是输出差，s_out是借位输出，sub_in是借位输入。(2)以1位全减器为基本硬件，构成串行借位的8位减法器，要求用例化语句来完成此项设计(减法运算是x–y-sun_in=diffr)3-5.答案底层文件1：or2a.VHD实现或门操作LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYor2aISPORT(a,b:INSTD_LOGIC;c:OUTSTD_LOGIC);ENDENTITYor2a;ARCHITECTUREoneOFor2aISBEGINc=aORb;ENDARCHITECTUREone;底层文件2：h_subber.VHD实现一位半减器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYh_subberISPORT(x,y:INSTD_LOGIC;diff,s_out::OUTSTD_LOGIC);ENDENTITYh_subber;ARCHITECTUREONEOFh_subberISSIGNALxyz:STD_LOGIC_VECTOR(1DOWNTO0);BEGINxyz=x&y;PROCESS(xyz)BEGINCASExyzISWHEN00=diff='0';s_out='0';WHEN01=diff='1';s_out='1';WHEN10=diff='1';s_out='0';WHEN11=diff='0';s_out='0';WHENOTHERS=NULL;ENDCASE;ENDPROCESS;ENDARCHITECTUREONE;顶层文件：f_subber.VHD实现一位全减器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYf_subberISPORT(x,y,sub_in:INSTD_LOGIC;diffr,sub_out:OUTSTD_LOGIC);ENDENTITYf_subber;ARCHITECTUREONEOFf_subberISCOMPONENTh_subberPORT(x,y:INSTD_LOGIC;diff,S_out:OUTSTD_LOGIC);ENDCOMPONENT;COMPONENTor2aPORT(a,b:INSTD_LOGIC;c:OUTSTD_LOGIC);ENDCOMPONENT;SIGNALd,e,f:STD_LOGIC;BEGINu1:h_subberPORTMAP(x=x,y=y,diff=d,s_out=e);u2:h_subberPORTMAP(x=d,y=sub_in,diff=diffr,s_out=f);u3:or2aPORTMAP(a=f,b=e,c=sub_out);ENDARCHITECTUREONE;ENDARCHITECTUREART;3-6.根据下图，写出顶层文件MX3256.VHD的VHDL设计文件。3-6.答案MAX3256顶层文件LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYMAX3256ISPORT(INA,INB,INCK:INSTD_LOGIC;INC:INSTD_LOGIC;E,OUT:OUTSTD_LOGIC);ENDENTITYMAX3256;ARCHITECTUREONEOFMAX3256ISCOMPONENTLK35--调用LK35声明语句PORT(A1,A2:INSTD_LOGIC;CLK:INSTD_LOGIC;Q1,Q2:OUTSTD_LOGIC);ENDCOMPONENT;COMPONENTD--调用D触发器声明语句PORT(D,C:INSTD_LOGIC;CLK:INSTD_LOGIC;Q:OUTSTD_LOGIC);ENDCOMPONENT;COMPONENTMUX21--调用二选一选择器声明语句PORT(B,A:INSTD_LOGIC;S:INSTD_LOGIC;C:OUTSTD_LOGIC);ENDCOMPONENT;SIGNALAA,BB,CC,DD:STD_LOGIC;BEGINu1:LK35PORTMAP(A1=INA,A2=INB,CLK=INCK,Q1=AA,Q2=BB);u2:DPORTMAP(D=BB;CLK=INCK,C=INC,Q=CC);u3:LK35PORTMAP(A1=BB,A2=CC,CLK=INCK,Q1=DD,Q2=OUT1)；u4:MUX21PORTMAP(B=AA,A=DD,S=BB,C=E);ENDARCHITECTUREONE;3-7设计含有异步清零和计数使能的16位二进制加减可控计数器。3-7.答案：LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCNT16ISPORT(CLK,RST,EN:INSTD_LOGIC;CHOOSE:INBIT;SETDATA:BUFFERINTEGERRANCE65535DOWNTO0;COUT:BUFFERINTEGERRANCE65535DOWNTO0);ENDCNT16;ARCHITECTUREONEOFCNT16ISBEGINPROCESS(CLK,RST,SDATA)VARIABLEQI:STD_LOGIC_VECTOR(65535DOWNTO0);BEGINIFRST='1'THEN--计数器异步复位QI:=(OTHERS='0');ELSIFSET=’1’THEN--计数器一步置位QI:=SETDATA;ELSIFCLK'EVENTANDCLK='1'THEN--检测时钟上升沿IFEN=’1’THEN–检测是否允许计数IFCHOOSE=’1’THEN--选择加法计数QI:=QI+1;--计数器加一ELSEQI=QI-1;--计数器加一ENDIF;ENDIF;ENDIF;COUT=QI;--将计数值向端口输出ENDPROCESS;ENDONE;3-13程序1：SIGNALA,EN:STD_LOGIC;PROCESS(A,EN)VARIABLEB:STD_LOGIC;BEGINIFEN=‘1’THENB:=A;ENDIF;ENDPROCESS;程序2：ARCHITECTUREoneOFsampleISVARIABLEa,b,c:BEGINc:=a+b;ENDARCHITECTUREone;程序3：LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYmux21ISPORT(a,b:INSTD_LOGIC;sel:INSTD_LOGIC;c:OUTSTD_LOGIC);ENDENTITYmux21;ARCHITECTUREoneOFmux21ISBEGINIFsel=‘0’T