Verilog--RS触发器

moduleSY_RS_FF(R,S,CLK,Q,QB);//庁翠兆式歌方協吶・袈律崛endmodule。inputR,S,CLK;//補秘極笥協吶outputQ,QB;//補竃極笥協吶regQ;//篠贋匂協吶assignQB=~Q;//assign囂鞘・QB=/Q。always@(posedgeCLK)//壓CLK議貧柳冽・峇佩參和囂鞘。case({R,S})//case囂鞘・崛噐endcase葎峭。1:Q=1;//輝R,S議怏栽葎01・夸綜Q=1。2:Q=0;//輝R,S議怏栽葎01・夸綜Q=1。3:Q=1'bx;//輝R,S議怏栽葎11・夸綜Q葎1bit議方・方峙葎音協(x)。endcase//case囂鞘潤崩endmodule