ST92250R2QB中文资料

November20041/426Rev.4.0ST92F124/ST92F150/ST92F2508/16-BITSINGLEVOLTAGEFLASHMCUFAMILYWITHRAM,E3TM(EMULATEDEEPROM),CAN2.0BANDJ1850BLPD■Memories–InternalMemory:SingleVoltageFLASHupto256Kbytes,RAMupto8Kbytes,1KbyteE3TM(Emulat-edEEPROM)–In-ApplicationProgramming(IAP)–224generalpurposeregisters(registerfile)availa-bleasRAM,accumulatorsorindexpointers■Clock,ResetandSupplyManagement–Register-oriented8/16bitCOREwithRUN,WFI,SLOW,HALTandSTOPmodes–0-24MHzOperation(Int.Clock),4.5-5.5Vrange–PLLClockGenerator(3-5MHzcrystal)–Minimuminstructiontime:83ns(24MHzint.clock)■Upto80I/Opins■InterruptManagement–4externalfastinterrupts+1NMI–Upto16pinsprogrammableaswake-uporaddition-alexternalinterruptwithmulti-levelinterrupthandler■DMAcontrollerforreducedprocessoroverhead■Timers–16-bitTimerwith8-bitPrescaler,andWatchdogTim-er(activatedbysoftwareorbyhardware)–16-bitStandardTimerthatcanbeusedtogenerateatimebaseindependentofPLLClockGenerator–Two16-bitindependentExtendedFunctionTimers(EFTs)withPrescaler,uptotwoInputCapturesanduptotwoOutputCompares–Two16-bitMultifunctionTimers,withPrescaler,uptotwoInputCapturesanduptotwoOutputCom-pares■CommunicationInterfaces–SerialPeripheralInterface(SPI)withSelectableMaster/Slavemode–OneMultiprotocolSerialCommunicationsInterfacewithasynchronousandsynchronouscapabilities–OneasynchronousSerialCommunicationsInterfacewith13-bitLINSynchBreakgenerationcapability–J1850ByteLevelProtocolDecoder(JBLPD)–UptotwofullI²CmultipleMaster/SlaveInterfacessupportingAccessBus–UptotwoCAN2.0BActiveinterfaces■Analogperipheral(lowcurrentcoupling)–10-bitA/DConverterwitvalhupto16robustinputchannels■DevelopmentTools–FreeHighperformanceDevelopmentenvironment(IDE)basedonVisualDebugger,Assembler,Linker,andC-Compiler;RealTimeOperatingSystem(OS-EKOS,CMX)andCANdrivers–HardwareEmulatorandFlashProgrammingBoardfordevelopmentandISPFlasherforproductionDEVICESUMMARY2)1)seeSection12.4onpage406forimportantinformation2)seeTable71onpage403forthelistofsupportedpartnumbersPQFP10014x20TQFP6414x14TQFP10014x14FeaturesST92F124R9ST92F124V1ST92F150CR9/1ST92F150CV9/1ST92F150JDV1ST92F250CV2FLASH-bytes64K128K64K/128K64K/128K128K256KRAM-bytes2K4K2K/4K2K/4K6K8KE3TM-bytes1K1K1K1K1K1KTimersandSerialInterface2MFT,2EFT,STIM,WD,SCI,SPI,I²C2MFT,2EFT,STIM,WD,2SCI,SPI,I²C2MFT,2EFT,STIM,WD,SCI,SPI,I²C2MFT,2EFT,STIM,WD,2SCI,SPI,I²C2MFT,2EFT,STIM,WD,2SCI,SPI,I²C2MFT,2EFT,STIM,WD,2SCI,SPI,2I²C1)ADC16x10bits16x10bits16x10bits16x10bits16x10bits16x10bitsNetworkInter-face-LINMasterCANCAN,LINMaster2CAN,J1850,LINMasterCAN,LINMasterPackagesTQFP64P/TQFP100TQFP64P/TQFP100P/TQFP10092/426TableofContents42691GENERALDESCRIPTION......................................................41.1INTRODUCTION........................................................41.2PINDESCRIPTION.....................................................101.3VOLTAGEREGULATOR................................................221.4I/OPORTS............................................................231.5ALTERNATEFUNCTIONSFORI/OPORTS.................................251.6OPERATINGMODES...................................................292DEVICEARCHITECTURE.....................................................302.1COREARCHITECTURE.................................................302.2MEMORYSPACES.....................................................302.3SYSTEMREGISTERS..................................................332.4MEMORYORGANIZATION..............................................412.5MEMORYMANAGEMENTUNIT..........................................422.6ADDRESSSPACEEXTENSION..........................................432.7MMUREGISTERS.....................................................442.8MMUUSAGE..........................................................483SINGLEVOLTAGEFLASH&E3TM(EMULATEDEEPROM).........................493.1INTRODUCTION.......................................................493.2FUNCTIONALDESCRIPTION............................................513.3REGISTERDESCRIPTION...............................................553.4WRITEOPERATIONEXAMPLE...........................................593.5PROTECTIONSTRATEGY...............................................603.6FLASHIN-SYSTEMPROGRAMMING......................................654REGISTERANDMEMORYMAP................................................674.1INTRODUCTION.......................................................674.2MEMORYCONFIGURATION.............................................674.3ST92F124/F150/F250REGISTERMAP.....................................735INTERRUPTS...............................................................915.1INTRODUCTION.......................................................915.2INTERRUPTVECTORING...............................................915.3INTERRUPTPRIORITYLEVELS..........................................935.4PRIORITYLEVELARBITRATION.........................................935.5ARBITRATIONMODES.................................................945.6EXTERNALINTERRUPTS...............................................995.7STANDARDINTERRUPTS(CANAN