基于FPGA-CPLD的通用异步通信接口UART的设计

FPGA/CPLDUARTTheDesignofUART(UniversalAsynchronousReceiverTransmitter)basedonFPGA/CPLD3JIANGNingFANDuo2wangUART()FPGA/CPLD,(EDA)FPGA/CPLDUART,UARTFPGA/CPLD,UART,VHDLQUARTUSIIUARTVHDLFPGA/CPLDAbstractUART(UniversalAsynchronousReceiverTransmitter)isashort2haulserialcommunicationinterfacewhichisappliedwidelyindigitalcommunicationandcontrolsystem.TheresultofLSI(LargeScaleIntegration)isFP2GA/CPLD,itistheattributeofsemi2customIntegrateCircuit,combiningEDAwithFPGA/CPLDwillconstructthedigi2talsystemquicklyandexpediently.Thisarticleintroducesamethodtodesignuartbasedontheprogrammablelogicde2viceFPGA/CPLD.ThecorefunctionofUARTisintegratedinFPGA/CPLD.ThisdesignincludestheTransmitterLog2ictheReceiverLogicandtheBaudrateGenerator.AllfunctionaregivenbyVHDL.Theimplementationofdesignsim2ulationsynthesisisthesoftwareofQUARTUSII.KeywordsUARTVHDLFPGA/CPLDSimulation3730070EDA,FPGA/CPLD,UART(UniversalAsynchronousReceiverTrans2mitter)UARTRS2322C,UART,82508251,,,UART1655016750,,UARTUARTFPGA/CPLDVHDLUART,,1UARTUART/1(idle,)(startbit,)58(databits)(paritybit,)(stopbit,11.52)UART,(58)(1,1.5,2),,8bitlbit1,;0,1UART2UART,UART,UART,22UART86200612.1UART,1,txd,CPU(THR),,,CPUTHR,THR(TSR):bigin1begin2:,;txdone7txdone8:78;Txdone=txdone8when8bitelsetxdone7;Paritycycle7paritycycle8:78;Parity=parity8when8bitelseparity7;Writerdy:0CPUTHR,1:txdonewriterdy,LOADTHRLOADTSR,,,txdone=1,,writerdy,,txdone,38bit16CLK161,18(8)1()1CPUtbr,CPUtbr,,,wen,din[7..0]tbr[7..0],tsr[7..0]douttre,,tre1,CPU33UART442.2UARTUARTrxd,,10,rxd10,08CLK16,,16CLK16,rsr,dout91011,,,,,,FRAMEhuntidle,hunt,idle,,idle,,(,),,,,2006187,RXFRAME,58bit(,)55UART62.31,UART()CPU,16,,,9600bps,960016Hz,1.8432MHz,CPU,,1843200/(16*),9600Hz,1843200/(169600)=12(0CH)3VHDLUARTclk,reset,rxd,rdwrcsa1a0count,txd,rdfulltdemptydataVHDLUART,,,ALTERAACEX1KEP1K30TC14423,FAGAUARTUART677:[1].cpu/soc(fpga/cpld).[M].:,2004[2],.eda[M].:,2002.10.[3],..[M](3)..,1994[4]ALTERA.a8251programmablecommunicationinterfacedatasheet.[A](:2005209212)8820061